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test: Make tests runnable on system without 4KiB page size (#5184)
* ARMeilleure: Do not hardcode 4KiB page size in JitCache * test: Do not hardcode page size to 4KiB for Ryujinx.Tests.Memory.Tests Fix running tests on Asahi Linux with 16KiB pages. * test: Do not hardcode page size to 4KiB for Ryujinx.Tests.Cpu Fix running tests on Asahi Linux. Test runner still crash when trying to run all test suite. * test: Do not hardcode page size to 4KiB for Ryujinx.Tests.Cpu Fix somecrashes on Asahi Linux. * test: Ignore Vshl test on ARM64 due to unicorn crashes * test: Workaround hardcoded size on some tests Change mapping of code and data in case of non 4KiB configuration. * test: Make CpuTestT32Flow depends on code address Fix failure with different page size. * test: Disable CpuTestThumb.TestRandomTestCases when page size isn't 4KiB The test data needs to be reevaluated to take different page size into account. * Address gdkchan's comments
This commit is contained in:
parent
105c9712c1
commit
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8 changed files with 93 additions and 47 deletions
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@ -2,6 +2,7 @@ using ARMeilleure.CodeGen;
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using ARMeilleure.CodeGen.Unwinding;
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using ARMeilleure.CodeGen.Unwinding;
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using ARMeilleure.Memory;
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using ARMeilleure.Memory;
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using ARMeilleure.Native;
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using ARMeilleure.Native;
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using Ryujinx.Memory;
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using System;
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using System;
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using System.Collections.Generic;
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using System.Collections.Generic;
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using System.Diagnostics;
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using System.Diagnostics;
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@ -12,8 +13,8 @@ namespace ARMeilleure.Translation.Cache
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{
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{
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static partial class JitCache
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static partial class JitCache
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{
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{
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private const int PageSize = 4 * 1024;
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private static readonly int PageSize = (int)MemoryBlock.GetPageSize();
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private const int PageMask = PageSize - 1;
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private static readonly int PageMask = PageSize - 1;
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private const int CodeAlignment = 4; // Bytes.
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private const int CodeAlignment = 4; // Bytes.
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private const int CacheSize = 2047 * 1024 * 1024;
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private const int CacheSize = 2047 * 1024 * 1024;
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@ -7,7 +7,7 @@ namespace Ryujinx.Tests.Memory
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{
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{
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public class Tests
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public class Tests
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{
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{
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private const ulong MemorySize = 0x8000;
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private static readonly ulong MemorySize = MemoryBlock.GetPageSize() * 8;
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private MemoryBlock _memoryBlock;
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private MemoryBlock _memoryBlock;
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@ -44,14 +44,17 @@ namespace Ryujinx.Tests.Memory
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[Platform(Exclude = "MacOsX")]
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[Platform(Exclude = "MacOsX")]
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public void Test_Alias()
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public void Test_Alias()
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{
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{
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using MemoryBlock backing = new MemoryBlock(0x10000, MemoryAllocationFlags.Mirrorable);
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ulong pageSize = MemoryBlock.GetPageSize();
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using MemoryBlock toAlias = new MemoryBlock(0x10000, MemoryAllocationFlags.Reserve | MemoryAllocationFlags.ViewCompatible);
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ulong blockSize = MemoryBlock.GetPageSize() * 16;
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toAlias.MapView(backing, 0x1000, 0, 0x4000);
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using MemoryBlock backing = new MemoryBlock(blockSize, MemoryAllocationFlags.Mirrorable);
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toAlias.UnmapView(backing, 0x3000, 0x1000);
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using MemoryBlock toAlias = new MemoryBlock(blockSize, MemoryAllocationFlags.Reserve | MemoryAllocationFlags.ViewCompatible);
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toAlias.MapView(backing, pageSize, 0, pageSize * 4);
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toAlias.UnmapView(backing, pageSize * 3, pageSize);
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toAlias.Write(0, 0xbadc0de);
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toAlias.Write(0, 0xbadc0de);
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Assert.AreEqual(Marshal.ReadInt32(backing.Pointer, 0x1000), 0xbadc0de);
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Assert.AreEqual(Marshal.ReadInt32(backing.Pointer, (int)pageSize), 0xbadc0de);
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}
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}
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[Test]
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[Test]
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@ -59,8 +62,12 @@ namespace Ryujinx.Tests.Memory
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[Platform(Exclude = "MacOsX")]
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[Platform(Exclude = "MacOsX")]
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public void Test_AliasRandom()
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public void Test_AliasRandom()
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{
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{
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using MemoryBlock backing = new MemoryBlock(0x80000, MemoryAllocationFlags.Mirrorable);
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ulong pageSize = MemoryBlock.GetPageSize();
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using MemoryBlock toAlias = new MemoryBlock(0x80000, MemoryAllocationFlags.Reserve | MemoryAllocationFlags.ViewCompatible);
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int pageBits = (int)ulong.Log2(pageSize);
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ulong blockSize = MemoryBlock.GetPageSize() * 128;
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using MemoryBlock backing = new MemoryBlock(blockSize, MemoryAllocationFlags.Mirrorable);
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using MemoryBlock toAlias = new MemoryBlock(blockSize, MemoryAllocationFlags.Reserve | MemoryAllocationFlags.ViewCompatible);
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Random rng = new Random(123);
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Random rng = new Random(123);
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@ -72,16 +79,16 @@ namespace Ryujinx.Tests.Memory
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if ((rng.Next() & 1) != 0)
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if ((rng.Next() & 1) != 0)
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{
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{
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toAlias.MapView(backing, (ulong)srcPage << 12, (ulong)dstPage << 12, (ulong)pages << 12);
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toAlias.MapView(backing, (ulong)srcPage << pageBits, (ulong)dstPage << pageBits, (ulong)pages << pageBits);
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int offset = rng.Next(0, 0x1000 - sizeof(int));
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int offset = rng.Next(0, (int)pageSize - sizeof(int));
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toAlias.Write((ulong)((dstPage << 12) + offset), 0xbadc0de);
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toAlias.Write((ulong)((dstPage << pageBits) + offset), 0xbadc0de);
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Assert.AreEqual(Marshal.ReadInt32(backing.Pointer, (srcPage << 12) + offset), 0xbadc0de);
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Assert.AreEqual(Marshal.ReadInt32(backing.Pointer, (srcPage << pageBits) + offset), 0xbadc0de);
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}
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}
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else
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else
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{
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{
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toAlias.UnmapView(backing, (ulong)dstPage << 12, (ulong)pages << 12);
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toAlias.UnmapView(backing, (ulong)dstPage << pageBits, (ulong)pages << pageBits);
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}
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}
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}
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}
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}
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}
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@ -91,7 +98,7 @@ namespace Ryujinx.Tests.Memory
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[Platform(Exclude = "MacOsX")]
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[Platform(Exclude = "MacOsX")]
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public void Test_AliasMapLeak()
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public void Test_AliasMapLeak()
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{
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{
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ulong pageSize = 4096;
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ulong pageSize = MemoryBlock.GetPageSize();
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ulong size = 100000 * pageSize; // The mappings limit on Linux is usually around 65K, so let's make sure we are above that.
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ulong size = 100000 * pageSize; // The mappings limit on Linux is usually around 65K, so let's make sure we are above that.
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using MemoryBlock backing = new MemoryBlock(pageSize, MemoryAllocationFlags.Mirrorable);
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using MemoryBlock backing = new MemoryBlock(pageSize, MemoryAllocationFlags.Mirrorable);
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@ -13,9 +13,9 @@ namespace Ryujinx.Tests.Cpu
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[TestFixture]
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[TestFixture]
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public class CpuTest
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public class CpuTest
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{
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{
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protected const ulong Size = 0x1000;
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protected static readonly ulong Size = MemoryBlock.GetPageSize();
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protected const ulong CodeBaseAddress = 0x1000;
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protected static ulong CodeBaseAddress = Size;
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protected const ulong DataBaseAddress = CodeBaseAddress + Size;
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protected static ulong DataBaseAddress = CodeBaseAddress + Size;
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private static bool Ignore_FpcrFz = false;
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private static bool Ignore_FpcrFz = false;
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private static bool Ignore_FpcrDn = false;
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private static bool Ignore_FpcrDn = false;
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@ -39,12 +39,24 @@ namespace Ryujinx.Tests.Cpu
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[SetUp]
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[SetUp]
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public void Setup()
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public void Setup()
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{
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{
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_currAddress = CodeBaseAddress;
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int pageBits = (int)ulong.Log2(Size);
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_ram = new MemoryBlock(Size * 2);
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_ram = new MemoryBlock(Size * 2);
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_memory = new MemoryManager(_ram, 1ul << 16);
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_memory = new MemoryManager(_ram, 1ul << (pageBits + 4));
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_memory.IncrementReferenceCount();
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_memory.IncrementReferenceCount();
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_memory.Map(CodeBaseAddress, 0, Size * 2, MemoryMapFlags.Private);
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// Some tests depends on hardcoded address that were computed for 4KiB.
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// We change the layout on non 4KiB platforms to keep compat here.
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if (Size > 0x1000)
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{
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DataBaseAddress = 0;
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CodeBaseAddress = Size;
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}
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_currAddress = CodeBaseAddress;
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_memory.Map(CodeBaseAddress, 0, Size, MemoryMapFlags.Private);
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_memory.Map(DataBaseAddress, Size, Size, MemoryMapFlags.Private);
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_context = CpuContext.CreateExecutionContext();
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_context = CpuContext.CreateExecutionContext();
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Translator.IsReadyForTranslation.Set();
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Translator.IsReadyForTranslation.Set();
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@ -13,9 +13,9 @@ namespace Ryujinx.Tests.Cpu
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[TestFixture]
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[TestFixture]
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public class CpuTest32
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public class CpuTest32
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{
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{
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protected const uint Size = 0x1000;
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protected static readonly uint Size = (uint)MemoryBlock.GetPageSize();
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protected const uint CodeBaseAddress = 0x1000;
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protected static uint CodeBaseAddress = Size;
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protected const uint DataBaseAddress = CodeBaseAddress + Size;
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protected static uint DataBaseAddress = CodeBaseAddress + Size;
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private uint _currAddress;
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private uint _currAddress;
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@ -33,12 +33,24 @@ namespace Ryujinx.Tests.Cpu
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[SetUp]
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[SetUp]
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public void Setup()
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public void Setup()
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{
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{
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_currAddress = CodeBaseAddress;
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int pageBits = (int)ulong.Log2(Size);
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_ram = new MemoryBlock(Size * 2);
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_ram = new MemoryBlock(Size * 2);
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_memory = new MemoryManager(_ram, 1ul << 16);
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_memory = new MemoryManager(_ram, 1ul << (pageBits + 4));
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_memory.IncrementReferenceCount();
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_memory.IncrementReferenceCount();
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_memory.Map(CodeBaseAddress, 0, Size * 2, MemoryMapFlags.Private);
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// Some tests depends on hardcoded address that were computed for 4KiB.
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// We change the layout on non 4KiB platforms to keep compat here.
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if (Size > 0x1000)
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{
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DataBaseAddress = 0;
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CodeBaseAddress = Size;
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}
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_currAddress = CodeBaseAddress;
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_memory.Map(CodeBaseAddress, 0, Size, MemoryMapFlags.Private);
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_memory.Map(DataBaseAddress, Size, Size, MemoryMapFlags.Private);
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_context = CpuContext.CreateExecutionContext();
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_context = CpuContext.CreateExecutionContext();
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_context.IsAarch32 = true;
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_context.IsAarch32 = true;
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@ -1,6 +1,7 @@
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#define SimdMemory32
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#define SimdMemory32
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using ARMeilleure.State;
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using ARMeilleure.State;
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using Ryujinx.Memory;
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using NUnit.Framework;
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using NUnit.Framework;
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using System;
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using System;
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[Category("SimdMemory32")]
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[Category("SimdMemory32")]
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public sealed class CpuTestSimdMemory32 : CpuTest32
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public sealed class CpuTestSimdMemory32 : CpuTest32
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{
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{
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private static readonly uint TestOffset = DataBaseAddress + 0x500;
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#if SimdMemory32
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#if SimdMemory32
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private uint[] _ldStModes =
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private uint[] _ldStModes =
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[Range(0u, 3u)] uint n,
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[Range(0u, 3u)] uint n,
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[Values(0x0u)] uint offset)
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[Values(0x0u)] uint offset)
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{
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{
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var data = GenerateVectorSequence(0x1000);
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var data = GenerateVectorSequence((int)MemoryBlock.GetPageSize());
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SetWorkingMemory(0, data);
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SetWorkingMemory(0, data);
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uint opcode = 0xf4a00000u; // VLD1.8 {D0[0]}, [R0], R0
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uint opcode = 0xf4a00000u; // VLD1.8 {D0[0]}, [R0], R0
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opcode |= (n & 3) << 8; // LD1 is 0, LD2 is 1 etc.
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opcode |= (n & 3) << 8; // LD1 is 0, LD2 is 1 etc.
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SingleOpcode(opcode, r0: 0x2500, r1: offset, sp: 0x2500);
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SingleOpcode(opcode, r0: TestOffset, r1: offset, sp: TestOffset);
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CompareAgainstUnicorn();
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CompareAgainstUnicorn();
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}
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}
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[Values] bool t,
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[Values] bool t,
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[Values(0x0u)] uint offset)
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[Values(0x0u)] uint offset)
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{
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{
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var data = GenerateVectorSequence(0x1000);
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var data = GenerateVectorSequence((int)MemoryBlock.GetPageSize());
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SetWorkingMemory(0, data);
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SetWorkingMemory(0, data);
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uint opcode = 0xf4a00c00u; // VLD1.8 {D0[0]}, [R0], R0
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uint opcode = 0xf4a00c00u; // VLD1.8 {D0[0]}, [R0], R0
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opcode |= (n & 3) << 8; // LD1 is 0, LD2 is 1 etc.
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opcode |= (n & 3) << 8; // LD1 is 0, LD2 is 1 etc.
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if (t) opcode |= 1 << 5;
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if (t) opcode |= 1 << 5;
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SingleOpcode(opcode, r0: 0x2500, r1: offset, sp: 0x2500);
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SingleOpcode(opcode, r0: TestOffset, r1: offset, sp: TestOffset);
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CompareAgainstUnicorn();
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CompareAgainstUnicorn();
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}
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}
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[Range(0u, 10u)] uint mode,
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[Range(0u, 10u)] uint mode,
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[Values(0x0u)] uint offset)
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[Values(0x0u)] uint offset)
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{
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{
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var data = GenerateVectorSequence(0x1000);
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var data = GenerateVectorSequence((int)MemoryBlock.GetPageSize());
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SetWorkingMemory(0, data);
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SetWorkingMemory(0, data);
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uint opcode = 0xf4200000u; // VLD4.8 {D0, D1, D2, D3}, [R0], R0
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uint opcode = 0xf4200000u; // VLD4.8 {D0, D1, D2, D3}, [R0], R0
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opcode |= ((vd & 0x10) << 18);
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opcode |= ((vd & 0x10) << 18);
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opcode |= ((vd & 0xf) << 12);
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opcode |= ((vd & 0xf) << 12);
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SingleOpcode(opcode, r0: 0x2500, r1: offset, sp: 0x2500);
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SingleOpcode(opcode, r0: TestOffset, r1: offset, sp: TestOffset);
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CompareAgainstUnicorn();
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CompareAgainstUnicorn();
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}
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}
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[Range(0u, 3u)] uint n,
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[Range(0u, 3u)] uint n,
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[Values(0x0u)] uint offset)
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[Values(0x0u)] uint offset)
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{
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{
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var data = GenerateVectorSequence(0x1000);
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var data = GenerateVectorSequence((int)MemoryBlock.GetPageSize());
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SetWorkingMemory(0, data);
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SetWorkingMemory(0, data);
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(V128 vec1, V128 vec2, V128 vec3, V128 vec4) = GenerateTestVectors();
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(V128 vec1, V128 vec2, V128 vec3, V128 vec4) = GenerateTestVectors();
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opcode |= (n & 3) << 8; // ST1 is 0, ST2 is 1 etc.
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opcode |= (n & 3) << 8; // ST1 is 0, ST2 is 1 etc.
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SingleOpcode(opcode, r0: 0x2500, r1: offset, v1: vec1, v2: vec2, v3: vec3, v4: vec4, sp: 0x2500);
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SingleOpcode(opcode, r0: TestOffset, r1: offset, v1: vec1, v2: vec2, v3: vec3, v4: vec4, sp: TestOffset);
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CompareAgainstUnicorn();
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CompareAgainstUnicorn();
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}
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}
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[Range(0u, 10u)] uint mode,
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[Range(0u, 10u)] uint mode,
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[Values(0x0u)] uint offset)
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[Values(0x0u)] uint offset)
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{
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{
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var data = GenerateVectorSequence(0x1000);
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var data = GenerateVectorSequence((int)MemoryBlock.GetPageSize());
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SetWorkingMemory(0, data);
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SetWorkingMemory(0, data);
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(V128 vec1, V128 vec2, V128 vec3, V128 vec4) = GenerateTestVectors();
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(V128 vec1, V128 vec2, V128 vec3, V128 vec4) = GenerateTestVectors();
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opcode |= ((vd & 0x10) << 18);
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opcode |= ((vd & 0x10) << 18);
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opcode |= ((vd & 0xf) << 12);
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opcode |= ((vd & 0xf) << 12);
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SingleOpcode(opcode, r0: 0x2500, r1: offset, v1: vec1, v2: vec2, v3: vec3, v4: vec4, sp: 0x2500);
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SingleOpcode(opcode, r0: TestOffset, r1: offset, v1: vec1, v2: vec2, v3: vec3, v4: vec4, sp: TestOffset);
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CompareAgainstUnicorn();
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CompareAgainstUnicorn();
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}
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}
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[Values(0x1u, 0x32u)] uint regs,
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[Values(0x1u, 0x32u)] uint regs,
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[Values] bool single)
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[Values] bool single)
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{
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{
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var data = GenerateVectorSequence(0x1000);
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var data = GenerateVectorSequence((int)MemoryBlock.GetPageSize());
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SetWorkingMemory(0, data);
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SetWorkingMemory(0, data);
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uint opcode = 0xec100a00u; // VST4.8 {D0, D1, D2, D3}, [R0], R0
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uint opcode = 0xec100a00u; // VST4.8 {D0, D1, D2, D3}, [R0], R0
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||||||
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@ -225,7 +227,7 @@ namespace Ryujinx.Tests.Cpu
|
||||||
|
|
||||||
opcode |= regs & 0xff;
|
opcode |= regs & 0xff;
|
||||||
|
|
||||||
SingleOpcode(opcode, r0: 0x2500, sp: 0x2500);
|
SingleOpcode(opcode, r0: TestOffset, sp: TestOffset);
|
||||||
|
|
||||||
CompareAgainstUnicorn();
|
CompareAgainstUnicorn();
|
||||||
}
|
}
|
||||||
|
@ -237,7 +239,7 @@ namespace Ryujinx.Tests.Cpu
|
||||||
[Values(0x0u)] uint imm,
|
[Values(0x0u)] uint imm,
|
||||||
[Values] bool sub)
|
[Values] bool sub)
|
||||||
{
|
{
|
||||||
var data = GenerateVectorSequence(0x1000);
|
var data = GenerateVectorSequence((int)MemoryBlock.GetPageSize());
|
||||||
SetWorkingMemory(0, data);
|
SetWorkingMemory(0, data);
|
||||||
|
|
||||||
uint opcode = 0xed900a00u; // VLDR.32 S0, [R0, #0]
|
uint opcode = 0xed900a00u; // VLDR.32 S0, [R0, #0]
|
||||||
|
@ -260,7 +262,7 @@ namespace Ryujinx.Tests.Cpu
|
||||||
}
|
}
|
||||||
opcode |= imm & 0xff;
|
opcode |= imm & 0xff;
|
||||||
|
|
||||||
SingleOpcode(opcode, r0: 0x2500);
|
SingleOpcode(opcode, r0: TestOffset);
|
||||||
|
|
||||||
CompareAgainstUnicorn();
|
CompareAgainstUnicorn();
|
||||||
}
|
}
|
||||||
|
@ -272,7 +274,7 @@ namespace Ryujinx.Tests.Cpu
|
||||||
[Values(0x0u)] uint imm,
|
[Values(0x0u)] uint imm,
|
||||||
[Values] bool sub)
|
[Values] bool sub)
|
||||||
{
|
{
|
||||||
var data = GenerateVectorSequence(0x1000);
|
var data = GenerateVectorSequence((int)MemoryBlock.GetPageSize());
|
||||||
SetWorkingMemory(0, data);
|
SetWorkingMemory(0, data);
|
||||||
|
|
||||||
uint opcode = 0xed800a00u; // VSTR.32 S0, [R0, #0]
|
uint opcode = 0xed800a00u; // VSTR.32 S0, [R0, #0]
|
||||||
|
@ -297,7 +299,7 @@ namespace Ryujinx.Tests.Cpu
|
||||||
|
|
||||||
(V128 vec1, V128 vec2, _, _) = GenerateTestVectors();
|
(V128 vec1, V128 vec2, _, _) = GenerateTestVectors();
|
||||||
|
|
||||||
SingleOpcode(opcode, r0: 0x2500, v0: vec1, v1: vec2);
|
SingleOpcode(opcode, r0: TestOffset, v0: vec1, v1: vec2);
|
||||||
|
|
||||||
CompareAgainstUnicorn();
|
CompareAgainstUnicorn();
|
||||||
}
|
}
|
||||||
|
|
|
@ -3,6 +3,7 @@
|
||||||
using ARMeilleure.State;
|
using ARMeilleure.State;
|
||||||
using NUnit.Framework;
|
using NUnit.Framework;
|
||||||
using System.Collections.Generic;
|
using System.Collections.Generic;
|
||||||
|
using System.Runtime.InteropServices;
|
||||||
|
|
||||||
namespace Ryujinx.Tests.Cpu
|
namespace Ryujinx.Tests.Cpu
|
||||||
{
|
{
|
||||||
|
@ -703,6 +704,11 @@ namespace Ryujinx.Tests.Cpu
|
||||||
[Values] bool q,
|
[Values] bool q,
|
||||||
[Values] bool u)
|
[Values] bool u)
|
||||||
{
|
{
|
||||||
|
if (RuntimeInformation.ProcessArchitecture == Architecture.Arm64)
|
||||||
|
{
|
||||||
|
Assert.Ignore("Unicorn on ARM64 crash while executing this test");
|
||||||
|
}
|
||||||
|
|
||||||
uint opcode = 0xf2000400u; // VSHL.S8 D0, D0, D0
|
uint opcode = 0xf2000400u; // VSHL.S8 D0, D0, D0
|
||||||
if (q)
|
if (q)
|
||||||
{
|
{
|
||||||
|
|
|
@ -109,7 +109,7 @@ namespace Ryujinx.Tests.Cpu
|
||||||
|
|
||||||
ExecuteOpcodes(runUnicorn: false);
|
ExecuteOpcodes(runUnicorn: false);
|
||||||
|
|
||||||
Assert.That(GetContext().GetX(0), Is.EqualTo(0x1005));
|
Assert.That(GetContext().GetX(0), Is.EqualTo(CodeBaseAddress + 0x5));
|
||||||
}
|
}
|
||||||
|
|
||||||
[Test]
|
[Test]
|
||||||
|
@ -133,7 +133,7 @@ namespace Ryujinx.Tests.Cpu
|
||||||
|
|
||||||
ExecuteOpcodes(runUnicorn: false);
|
ExecuteOpcodes(runUnicorn: false);
|
||||||
|
|
||||||
Assert.That(GetContext().GetX(0), Is.EqualTo(0x1005));
|
Assert.That(GetContext().GetX(0), Is.EqualTo(CodeBaseAddress + 0x5));
|
||||||
Assert.That(GetContext().GetPstateFlag(PState.TFlag), Is.EqualTo(false));
|
Assert.That(GetContext().GetPstateFlag(PState.TFlag), Is.EqualTo(false));
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -160,7 +160,7 @@ namespace Ryujinx.Tests.Cpu
|
||||||
|
|
||||||
ExecuteOpcodes(runUnicorn: false);
|
ExecuteOpcodes(runUnicorn: false);
|
||||||
|
|
||||||
Assert.That(GetContext().GetX(0), Is.EqualTo(0x1007));
|
Assert.That(GetContext().GetX(0), Is.EqualTo(CodeBaseAddress + 0x7));
|
||||||
Assert.That(GetContext().GetPstateFlag(PState.TFlag), Is.EqualTo(false));
|
Assert.That(GetContext().GetPstateFlag(PState.TFlag), Is.EqualTo(false));
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
|
@ -268,6 +268,12 @@ namespace Ryujinx.Tests.Cpu
|
||||||
[Test]
|
[Test]
|
||||||
public void TestRandomTestCases([ValueSource(nameof(RandomTestCases))] PrecomputedThumbTestCase test)
|
public void TestRandomTestCases([ValueSource(nameof(RandomTestCases))] PrecomputedThumbTestCase test)
|
||||||
{
|
{
|
||||||
|
if (Size != 0x1000)
|
||||||
|
{
|
||||||
|
// TODO: Change it to depend on DataBaseAddress instead.
|
||||||
|
Assert.Ignore("This test currently only support 4KiB page size");
|
||||||
|
}
|
||||||
|
|
||||||
RunPrecomputedTestCase(test);
|
RunPrecomputedTestCase(test);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
Loading…
Reference in a new issue