mirror of
https://github.com/ryujinx-mirror/ryujinx.git
synced 2024-12-23 02:45:45 +00:00
Implement IMUL, PCNT and CONT shader instructions, fix FFMA32I and HFMA32I (#2972)
* Implement IMUL shader instruction * Implement PCNT/CONT instruction and fix FFMA32I * Add HFMA232I to the table * Shader cache version bump * No Rc on Ffma32i
This commit is contained in:
parent
952c6e4d45
commit
7f6b3d234a
9 changed files with 108 additions and 68 deletions
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@ -40,7 +40,7 @@ namespace Ryujinx.Graphics.Gpu.Shader
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/// <summary>
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/// Version of the codegen (to be changed when codegen or guest format change).
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/// </summary>
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private const ulong ShaderCodeGenVersion = 2764;
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private const ulong ShaderCodeGenVersion = 2972;
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// Progress reporting helpers
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private volatile int _shaderCount;
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@ -95,7 +95,7 @@ namespace Ryujinx.Graphics.Shader.Decoders
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if (currBlock.OpCodes.Count != 0)
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{
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// We should have blocks for all possible branch targets,
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// including those from SSY/PBK instructions.
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// including those from PBK/PCNT/SSY instructions.
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foreach (PushOpInfo pushOp in currBlock.PushOpCodes)
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{
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GetBlock(pushOp.Op.GetAbsoluteAddress());
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@ -243,7 +243,7 @@ namespace Ryujinx.Graphics.Shader.Decoders
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{
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SetUserAttributeUses(config, op.Name, opCode);
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}
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else if (op.Name == InstName.Ssy || op.Name == InstName.Pbk)
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else if (op.Name == InstName.Pbk || op.Name == InstName.Pcnt || op.Name == InstName.Ssy)
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{
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block.AddPushOp(op);
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}
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@ -512,8 +512,9 @@ namespace Ryujinx.Graphics.Shader.Decoders
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private enum MergeType
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{
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Brk = 0,
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Sync = 1
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Brk,
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Cont,
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Sync
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}
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private struct PathBlockState
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@ -629,7 +630,7 @@ namespace Ryujinx.Graphics.Shader.Decoders
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for (int index = pushOpIndex; index < pushOpsCount; index++)
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{
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InstOp currentPushOp = current.PushOpCodes[index].Op;
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MergeType pushMergeType = currentPushOp.Name == InstName.Ssy ? MergeType.Sync : MergeType.Brk;
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MergeType pushMergeType = GetMergeTypeFromPush(currentPushOp.Name);
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branchStack.Push((currentPushOp.GetAbsoluteAddress(), pushMergeType));
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}
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}
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@ -643,9 +644,9 @@ namespace Ryujinx.Graphics.Shader.Decoders
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}
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InstOp lastOp = current.GetLastOp();
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if (lastOp.Name == InstName.Sync || lastOp.Name == InstName.Brk)
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if (IsPopBranch(lastOp.Name))
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{
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MergeType popMergeType = lastOp.Name == InstName.Sync ? MergeType.Sync : MergeType.Brk;
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MergeType popMergeType = GetMergeTypeFromPop(lastOp.Name);
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bool found = true;
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ulong targetAddress = 0UL;
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@ -662,7 +663,7 @@ namespace Ryujinx.Graphics.Shader.Decoders
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(targetAddress, mergeType) = branchStack.Pop();
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// Push the target address (this will be used to push the address
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// back into the SSY/PBK stack when we return from that block),
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// back into the PBK/PCNT/SSY stack when we return from that block),
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Push(new PathBlockState(targetAddress, mergeType));
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}
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while (mergeType != popMergeType);
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@ -705,5 +706,30 @@ namespace Ryujinx.Graphics.Shader.Decoders
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}
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}
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}
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public static bool IsPopBranch(InstName name)
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{
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return name == InstName.Brk || name == InstName.Cont || name == InstName.Sync;
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}
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private static MergeType GetMergeTypeFromPush(InstName name)
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{
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return name switch
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{
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InstName.Pbk => MergeType.Brk,
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InstName.Pcnt => MergeType.Cont,
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_ => MergeType.Sync
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};
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}
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private static MergeType GetMergeTypeFromPop(InstName name)
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{
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return name switch
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{
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InstName.Brk => MergeType.Brk,
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InstName.Cont => MergeType.Cont,
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_ => MergeType.Sync
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};
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}
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}
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}
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@ -1960,7 +1960,6 @@ namespace Ryujinx.Graphics.Shader.Decoders
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public int Dest => (int)((_opcode >> 0) & 0xFF);
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public int SrcA => (int)((_opcode >> 8) & 0xFF);
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public int Imm32 => (int)(_opcode >> 20);
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public int SrcC => (int)((_opcode >> 39) & 0xFF);
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public int Pred => (int)((_opcode >> 16) & 0x7);
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public bool PredInv => (_opcode & 0x80000) != 0;
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public bool NegC => (_opcode & 0x200000000000000) != 0;
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@ -2460,7 +2459,6 @@ namespace Ryujinx.Graphics.Shader.Decoders
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public int Dest => (int)((_opcode >> 0) & 0xFF);
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public int SrcA => (int)((_opcode >> 8) & 0xFF);
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public int Imm => (int)(_opcode >> 20);
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public int SrcC => (int)((_opcode >> 39) & 0xFF);
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public HalfSwizzle ASwizzle => (HalfSwizzle)((_opcode >> 47) & 0x3);
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public int Pred => (int)((_opcode >> 16) & 0x7);
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public bool PredInv => (_opcode & 0x80000) != 0;
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@ -55,7 +55,7 @@ namespace Ryujinx.Graphics.Shader.Decoders
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Add("1110111110000xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx", InstName.Cctll, InstEmit.Cctll, InstProps.Ra);
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Add("1110101111110xx0000000000000xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx", InstName.Cctlt, InstEmit.Cctlt);
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Add("1110101111101xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx", InstName.Cctlt, InstEmit.Cctlt, InstProps.Rc);
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Add("111000110101xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx", InstName.Cont, InstEmit.Cont);
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Add("111000110101xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx", InstName.Cont, InstEmit.Cont, InstProps.Bra);
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Add("0101000010011xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx", InstName.Cset, InstEmit.Cset, InstProps.Rd | InstProps.Ps);
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Add("0101000010100xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx", InstName.Csetp, InstEmit.Csetp, InstProps.Pd | InstProps.Pdn | InstProps.Ps);
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Add("0101000011001xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx", InstName.Cs2r, InstEmit.Cs2r, InstProps.Rd);
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@ -101,7 +101,7 @@ namespace Ryujinx.Graphics.Shader.Decoders
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Add("0011001x1xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx", InstName.Ffma, InstEmit.FfmaI, InstProps.Rd | InstProps.Ra | InstProps.Ib | InstProps.Rc);
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Add("010010011xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx", InstName.Ffma, InstEmit.FfmaC, InstProps.Rd | InstProps.Ra | InstProps.Rc);
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Add("010100011xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx", InstName.Ffma, InstEmit.FfmaRc, InstProps.Rd | InstProps.Ra | InstProps.Rc);
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Add("000011xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx", InstName.Ffma32i, InstEmit.Ffma32i, InstProps.Rd | InstProps.Ra | InstProps.Rc);
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Add("000011xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx", InstName.Ffma32i, InstEmit.Ffma32i, InstProps.Rd | InstProps.Ra);
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Add("0101110000110xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx", InstName.Flo, InstEmit.FloR, InstProps.Rd | InstProps.Rb);
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Add("0011100x00110xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx", InstName.Flo, InstEmit.FloI, InstProps.Rd | InstProps.Ib);
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Add("0100110000110xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx", InstName.Flo, InstEmit.FloC, InstProps.Rd);
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@ -129,6 +129,7 @@ namespace Ryujinx.Graphics.Shader.Decoders
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Add("01110xxx0xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx", InstName.Hfma2, InstEmit.Hfma2I, InstProps.Rd | InstProps.Ra | InstProps.Ib | InstProps.Rc);
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Add("01110xxx1xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx", InstName.Hfma2, InstEmit.Hfma2C, InstProps.Rd | InstProps.Ra | InstProps.Rc);
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Add("01100xxx1xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx", InstName.Hfma2, InstEmit.Hfma2Rc, InstProps.Rd | InstProps.Ra | InstProps.Rc);
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Add("0010100xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx", InstName.Hfma2, InstEmit.Hfma232i, InstProps.Rd | InstProps.Ra);
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Add("0101110100001xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx", InstName.Hmul2, InstEmit.Hmul2R, InstProps.Rd | InstProps.Ra | InstProps.Rb);
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Add("0111100x0xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx", InstName.Hmul2, InstEmit.Hmul2I, InstProps.Rd | InstProps.Ra | InstProps.Ib);
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Add("0111100x1xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx", InstName.Hmul2, InstEmit.Hmul2C, InstProps.Rd | InstProps.Ra);
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@ -54,18 +54,11 @@ namespace Ryujinx.Graphics.Shader.Instructions
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context.Config.GpuAccessor.Log("Shader instruction Cctlt is not implemented.");
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}
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public static void Cont(EmitterContext context)
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{
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InstCont op = context.GetOp<InstCont>();
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context.Config.GpuAccessor.Log("Shader instruction ContUnsup is not implemented.");
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}
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public static void Cset(EmitterContext context)
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{
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InstCset op = context.GetOp<InstCset>();
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context.Config.GpuAccessor.Log("Shader instruction CsetUnsup is not implemented.");
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context.Config.GpuAccessor.Log("Shader instruction Cset is not implemented.");
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}
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public static void Cs2r(EmitterContext context)
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@ -159,34 +152,6 @@ namespace Ryujinx.Graphics.Shader.Instructions
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context.Config.GpuAccessor.Log("Shader instruction ImadspRc is not implemented.");
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}
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public static void ImulR(EmitterContext context)
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{
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InstImulR op = context.GetOp<InstImulR>();
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context.Config.GpuAccessor.Log("Shader instruction ImulR is not implemented.");
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}
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public static void ImulI(EmitterContext context)
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{
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InstImulI op = context.GetOp<InstImulI>();
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context.Config.GpuAccessor.Log("Shader instruction ImulI is not implemented.");
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}
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public static void ImulC(EmitterContext context)
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{
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InstImulC op = context.GetOp<InstImulC>();
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context.Config.GpuAccessor.Log("Shader instruction ImulC is not implemented.");
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}
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public static void Imul32i(EmitterContext context)
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{
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InstImul32i op = context.GetOp<InstImul32i>();
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context.Config.GpuAccessor.Log("Shader instruction Imul32i is not implemented.");
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}
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public static void Jcal(EmitterContext context)
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{
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InstJcal op = context.GetOp<InstJcal>();
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context.Config.GpuAccessor.Log("Shader instruction P2rC is not implemented.");
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}
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public static void Pcnt(EmitterContext context)
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{
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InstPcnt op = context.GetOp<InstPcnt>();
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context.Config.GpuAccessor.Log("Shader instruction Pcnt is not implemented.");
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}
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public static void Pexit(EmitterContext context)
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{
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InstPexit op = context.GetOp<InstPexit>();
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@ -204,7 +204,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
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var srcA = GetSrcReg(context, op.SrcA);
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var srcB = GetSrcImm(context, op.Imm32);
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var srcC = GetSrcReg(context, op.SrcC);
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var srcC = GetSrcReg(context, op.Dest);
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EmitFfma(context, Instruction.FP32, srcA, srcB, srcC, op.Dest, op.NegA, op.NegC, op.Sat, op.WriteCC);
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}
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EmitHfma2(context, op.OFmt, srcA, srcB, srcC, op.Dest, op.Sat);
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}
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public static void Hfma232iI(EmitterContext context)
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public static void Hfma232i(EmitterContext context)
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{
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InstHfma232i op = context.GetOp<InstHfma232i>();
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var srcA = GetHalfSrc(context, op.ASwizzle, op.SrcA, false, false);
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var srcB = GetHalfSrc(context, op.Imm);
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var srcC = GetHalfSrc(context, HalfSwizzle.F16, op.SrcC, op.NegC, false);
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var srcC = GetHalfSrc(context, HalfSwizzle.F16, op.Dest, op.NegC, false);
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EmitHfma2(context, OFmt.F16, srcA, srcB, srcC, op.Dest, saturate: false);
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}
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@ -22,7 +22,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
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{
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InstBrk op = context.GetOp<InstBrk>();
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EmitBrkOrSync(context);
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EmitBrkContSync(context);
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}
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public static void Brx(EmitterContext context)
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@ -87,6 +87,13 @@ namespace Ryujinx.Graphics.Shader.Instructions
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}
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}
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public static void Cont(EmitterContext context)
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{
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InstCont op = context.GetOp<InstCont>();
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EmitBrkContSync(context);
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}
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public static void Exit(EmitterContext context)
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{
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InstExit op = context.GetOp<InstExit>();
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@ -116,7 +123,14 @@ namespace Ryujinx.Graphics.Shader.Instructions
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{
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InstPbk op = context.GetOp<InstPbk>();
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EmitPbkOrSsy(context);
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EmitPbkPcntSsy(context);
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}
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public static void Pcnt(EmitterContext context)
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{
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InstPcnt op = context.GetOp<InstPcnt>();
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EmitPbkPcntSsy(context);
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}
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public static void Ret(EmitterContext context)
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@ -137,17 +151,17 @@ namespace Ryujinx.Graphics.Shader.Instructions
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{
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InstSsy op = context.GetOp<InstSsy>();
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EmitPbkOrSsy(context);
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EmitPbkPcntSsy(context);
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}
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public static void Sync(EmitterContext context)
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{
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InstSync op = context.GetOp<InstSync>();
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EmitBrkOrSync(context);
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EmitBrkContSync(context);
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}
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private static void EmitPbkOrSsy(EmitterContext context)
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private static void EmitPbkPcntSsy(EmitterContext context)
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{
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var consumers = context.CurrBlock.PushOpCodes.First(x => x.Op.Address == context.CurrOp.Address).Consumers;
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@ -162,7 +176,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
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}
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}
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private static void EmitBrkOrSync(EmitterContext context)
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private static void EmitBrkContSync(EmitterContext context)
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{
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var targets = context.CurrBlock.SyncTargets;
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@ -138,6 +138,46 @@ namespace Ryujinx.Graphics.Shader.Instructions
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EmitImad(context, srcA, srcB, srcC, op.Dest, op.AvgMode, op.ASigned, op.BSigned, op.Hilo);
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}
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public static void ImulR(EmitterContext context)
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{
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InstImulR op = context.GetOp<InstImulR>();
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var srcA = GetSrcReg(context, op.SrcA);
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var srcB = GetSrcReg(context, op.SrcB);
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EmitImad(context, srcA, srcB, Const(0), op.Dest, AvgMode.NoNeg, op.ASigned, op.BSigned, op.Hilo);
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}
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public static void ImulI(EmitterContext context)
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{
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InstImulI op = context.GetOp<InstImulI>();
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var srcA = GetSrcReg(context, op.SrcA);
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var srcB = GetSrcImm(context, Imm20ToSInt(op.Imm20));
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EmitImad(context, srcA, srcB, Const(0), op.Dest, AvgMode.NoNeg, op.ASigned, op.BSigned, op.Hilo);
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}
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public static void ImulC(EmitterContext context)
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{
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InstImulC op = context.GetOp<InstImulC>();
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var srcA = GetSrcReg(context, op.SrcA);
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var srcB = GetSrcCbuf(context, op.CbufSlot, op.CbufOffset);
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EmitImad(context, srcA, srcB, Const(0), op.Dest, AvgMode.NoNeg, op.ASigned, op.BSigned, op.Hilo);
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}
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public static void Imul32i(EmitterContext context)
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{
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InstImul32i op = context.GetOp<InstImul32i>();
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var srcA = GetSrcReg(context, op.SrcA);
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var srcB = GetSrcImm(context, op.Imm32);
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EmitImad(context, srcA, srcB, Const(0), op.Dest, AvgMode.NoNeg, op.ASigned, op.BSigned, op.Hilo);
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}
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public static void IscaddR(EmitterContext context)
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{
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InstIscaddR op = context.GetOp<InstIscaddR>();
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@ -366,7 +406,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
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// TODO: CC, X, corner cases.
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}
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public static void EmitImad(
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private static void EmitImad(
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EmitterContext context,
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Operand srcA,
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Operand srcB,
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@ -407,7 +447,10 @@ namespace Ryujinx.Graphics.Shader.Instructions
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res = context.IMultiply(srcA, srcB);
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}
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res = context.IAdd(res, srcC);
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if (srcC.Type != OperandType.Constant || srcC.Value != 0)
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{
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res = context.IAdd(res, srcC);
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}
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// TODO: CC, X, SAT, and more?
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@ -295,7 +295,7 @@ namespace Ryujinx.Graphics.Shader.Translation
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Operand predSkipLbl = null;
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if (op.Name == InstName.Sync || op.Name == InstName.Brk)
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if (Decoder.IsPopBranch(op.Name))
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{
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// If the instruction is a SYNC or BRK instruction with only one
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// possible target address, then the instruction is basically
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