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Fix EXT/Widening instruction carrying garbage values on some cases, fix ABD (it shouldn't accumulate, this is another variation of the instruction)
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parent
76ac31add6
commit
916540ff41
3 changed files with 21 additions and 12 deletions
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@ -548,12 +548,12 @@ namespace ChocolArm64.Instruction
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public static void Uabd_V(AILEmitterCtx Context)
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{
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EmitVectorTernaryOpZx(Context, () => EmitAbd(Context));
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EmitVectorBinaryOpZx(Context, () => EmitAbd(Context));
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}
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public static void Uabdl_V(AILEmitterCtx Context)
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{
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EmitVectorWidenRnRmTernaryOpZx(Context, () => EmitAbd(Context));
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EmitVectorWidenRnRmBinaryOpZx(Context, () => EmitAbd(Context));
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}
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private static void EmitAbd(AILEmitterCtx Context)
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@ -563,8 +563,6 @@ namespace ChocolArm64.Instruction
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Type[] Types = new Type[] { typeof(long) };
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Context.EmitCall(typeof(Math).GetMethod(nameof(Math.Abs), Types));
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Context.Emit(OpCodes.Add);
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}
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public static void Uaddl_V(AILEmitterCtx Context)
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@ -447,6 +447,9 @@ namespace ChocolArm64.Instruction
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{
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AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp;
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Context.EmitLdvec(Op.Rd);
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Context.EmitStvectmp();
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int Elems = 8 >> Op.Size;
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int Part = Op.RegisterSize == ARegisterSize.SIMD128 ? Elems : 0;
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@ -489,6 +492,9 @@ namespace ChocolArm64.Instruction
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{
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AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp;
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Context.EmitLdvec(Op.Rd);
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Context.EmitStvectmp();
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int Elems = 8 >> Op.Size;
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int Part = Op.RegisterSize == ARegisterSize.SIMD128 ? Elems : 0;
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@ -61,6 +61,9 @@ namespace ChocolArm64.Instruction
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{
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AOpCodeSimdExt Op = (AOpCodeSimdExt)Context.CurrOp;
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Context.EmitLdvec(Op.Rd);
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Context.EmitStvectmp();
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int Bytes = Context.CurrOp.GetBitsCount() >> 3;
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int Position = Op.Imm4;
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@ -75,10 +78,12 @@ namespace ChocolArm64.Instruction
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}
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EmitVectorExtractZx(Context, Reg, Position++, 0);
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EmitVectorInsert(Context, Op.Rd, Index, 0);
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EmitVectorInsertTmp(Context, Index, 0);
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}
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Context.EmitLdvectmp();
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Context.EmitStvec(Op.Rd);
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if (Op.RegisterSize == ARegisterSize.SIMD64)
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{
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EmitVectorZeroUpper(Context, Op.Rd);
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@ -113,7 +118,7 @@ namespace ChocolArm64.Instruction
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EmitVectorExtractZx(Context, Op.Rn, 0, 3);
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EmitIntZeroHigherIfNeeded(Context);
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EmitIntZeroUpperIfNeeded(Context);
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Context.EmitStintzr(Op.Rd);
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}
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@ -124,7 +129,7 @@ namespace ChocolArm64.Instruction
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EmitVectorExtractZx(Context, Op.Rn, 1, 3);
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EmitIntZeroHigherIfNeeded(Context);
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EmitIntZeroUpperIfNeeded(Context);
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Context.EmitStintzr(Op.Rd);
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}
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@ -135,7 +140,7 @@ namespace ChocolArm64.Instruction
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Context.EmitLdintzr(Op.Rn);
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EmitIntZeroHigherIfNeeded(Context);
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EmitIntZeroUpperIfNeeded(Context);
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EmitScalarSet(Context, Op.Rd, 3);
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}
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@ -146,7 +151,7 @@ namespace ChocolArm64.Instruction
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Context.EmitLdintzr(Op.Rn);
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EmitIntZeroHigherIfNeeded(Context);
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EmitIntZeroUpperIfNeeded(Context);
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EmitVectorInsert(Context, Op.Rd, 1, 3);
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}
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@ -301,7 +306,7 @@ namespace ChocolArm64.Instruction
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EmitVectorZip(Context, Part: 1);
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}
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private static void EmitIntZeroHigherIfNeeded(AILEmitterCtx Context)
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private static void EmitIntZeroUpperIfNeeded(AILEmitterCtx Context)
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{
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if (Context.CurrOp.RegisterSize == ARegisterSize.Int32)
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{
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@ -322,7 +327,7 @@ namespace ChocolArm64.Instruction
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for (int Index = 0; Index < Elems; Index++)
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{
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int Elem = Part + ((Index & (Half - 1)) << 1);
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EmitVectorExtractZx(Context, Index < Half ? Op.Rn : Op.Rm, Elem, Op.Size);
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EmitVectorInsert(Context, Op.Rd, Index, Op.Size);
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