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Implement VORN (register) Arm32 instruction (#2396)
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commit
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4 changed files with 30 additions and 9 deletions
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@ -907,6 +907,7 @@ namespace ARMeilleure.Decoders
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SetA32("<<<<11100x01xxxxxxxx101xx1x0xxxx", InstName.Vnmla, InstEmit32.Vnmla_S, OpCode32SimdRegS.Create);
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SetA32("<<<<11100x01xxxxxxxx101xx0x0xxxx", InstName.Vnmls, InstEmit32.Vnmls_S, OpCode32SimdRegS.Create);
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SetA32("<<<<11100x10xxxxxxxx101xx1x0xxxx", InstName.Vnmul, InstEmit32.Vnmul_S, OpCode32SimdRegS.Create);
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SetA32("111100100x11xxxxxxxx0001xxx1xxxx", InstName.Vorn, InstEmit32.Vorn_I, OpCode32SimdBinary.Create);
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SetA32("111100100x10xxxxxxxx0001xxx1xxxx", InstName.Vorr, InstEmit32.Vorr_I, OpCode32SimdBinary.Create);
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SetA32("1111001x1x000xxxxxxx<<x10x01xxxx", InstName.Vorr, InstEmit32.Vorr_II, OpCode32SimdImm.Create);
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SetA32("111100100x<<xxxxxxxx1011x0x1xxxx", InstName.Vpadd, InstEmit32.Vpadd_I, OpCode32SimdReg.Create);
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@ -115,6 +115,24 @@ namespace ARMeilleure.Instructions
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}
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}
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public static void Vorn_I(ArmEmitterContext context)
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{
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if (Optimizations.UseSse2)
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{
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Operand mask = context.VectorOne();
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EmitVectorBinaryOpSimd32(context, (n, m) =>
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{
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m = context.AddIntrinsic(Intrinsic.X86Pandn, m, mask);
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return context.AddIntrinsic(Intrinsic.X86Por, n, m);
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});
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}
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else
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{
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EmitVectorBinaryOpZx32(context, (op1, op2) => context.BitwiseOr(op1, context.BitwiseNot(op2)));
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}
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}
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public static void Vorr_I(ArmEmitterContext context)
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{
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if (Optimizations.UseSse2)
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@ -605,6 +605,7 @@ namespace ARMeilleure.Instructions
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Vnmul,
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Vnmla,
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Vnmls,
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Vorn,
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Vorr,
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Vpadd,
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Vpmax,
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@ -22,7 +22,7 @@ namespace Ryujinx.Tests.Cpu
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#endregion
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#region "ValueSource (Opcodes)"
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private static uint[] _Vbic_Vbif_Vbit_Vbsl_Vand_Vorr_Veor_I_()
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private static uint[] _Vbic_Vbif_Vbit_Vbsl_Vand_Vorn_Vorr_Veor_I_()
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{
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return new uint[]
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{
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@ -31,6 +31,7 @@ namespace Ryujinx.Tests.Cpu
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0xf3200110u, // VBIT D0, D0, D0
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0xf3100110u, // VBSL D0, D0, D0
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0xf2000110u, // VAND D0, D0, D0
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0xf2300110u, // VORN D0, D0, D0
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0xf2200110u, // VORR D0, D0, D0
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0xf3000110u // VEOR D0, D0, D0
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};
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@ -51,14 +52,14 @@ namespace Ryujinx.Tests.Cpu
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private const int RndCnt = 2;
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[Test, Pairwise]
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public void Vbic_Vbif_Vbit_Vbsl_Vand_Vorr_Veor_I([ValueSource("_Vbic_Vbif_Vbit_Vbsl_Vand_Vorr_Veor_I_")] uint opcode,
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[Range(0u, 5u)] uint rd,
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[Range(0u, 5u)] uint rn,
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[Range(0u, 5u)] uint rm,
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[Values(ulong.MinValue, ulong.MaxValue)] [Random(RndCnt)] ulong z,
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[Values(ulong.MinValue, ulong.MaxValue)] [Random(RndCnt)] ulong a,
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[Values(ulong.MinValue, ulong.MaxValue)] [Random(RndCnt)] ulong b,
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[Values] bool q)
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public void Vbic_Vbif_Vbit_Vbsl_Vand_Vorn_Vorr_Veor_I([ValueSource("_Vbic_Vbif_Vbit_Vbsl_Vand_Vorn_Vorr_Veor_I_")] uint opcode,
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[Range(0u, 5u)] uint rd,
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[Range(0u, 5u)] uint rn,
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[Range(0u, 5u)] uint rm,
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[Values(ulong.MinValue, ulong.MaxValue)] [Random(RndCnt)] ulong z,
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[Values(ulong.MinValue, ulong.MaxValue)] [Random(RndCnt)] ulong a,
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[Values(ulong.MinValue, ulong.MaxValue)] [Random(RndCnt)] ulong b,
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[Values] bool q)
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{
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if (q)
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{
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