mirror of
https://github.com/ryujinx-mirror/ryujinx.git
synced 2024-12-22 13:25:47 +00:00
Move a few more SIMD instructions to emit CIL directly instead of a method call
This commit is contained in:
gdkchan
parent
12e263f8b2
commit
ccc9ce1908
7 changed files with 207 additions and 324 deletions
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@ -152,13 +152,13 @@ namespace ChocolArm64
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Set("x0011110xx110000000000xxxxxxxxxx", AInstEmit.Fcvtms_S, typeof(AOpCodeSimdCvt));
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Set("x0011110xx101000000000xxxxxxxxxx", AInstEmit.Fcvtps_S, typeof(AOpCodeSimdCvt));
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Set("x0011110xx111000000000xxxxxxxxxx", AInstEmit.Fcvtzs_S, typeof(AOpCodeSimdCvt));
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Set("0x0011101x100001101110xxxxxxxxxx", AInstEmit.Fcvtzs_V, typeof(AOpCodeSimd));
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Set("0x0011110>>xxxxx111111xxxxxxxxxx", AInstEmit.Fcvtzs_V_Fix, typeof(AOpCodeSimdShImm));
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Set("x0011110xx111001000000xxxxxxxxxx", AInstEmit.Fcvtzu_S, typeof(AOpCodeSimdCvt));
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Set("0x1011101x100001101110xxxxxxxxxx", AInstEmit.Fcvtzu_V, typeof(AOpCodeSimd));
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Set("0x1011110>>xxxxx111111xxxxxxxxxx", AInstEmit.Fcvtzu_V_Fix, typeof(AOpCodeSimdShImm));
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Set("x0011110xx011000xxxxxxxxxxxxxxxx", AInstEmit.Fcvtzs_Fix, typeof(AOpCodeSimdCvt));
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Set("0x0011101x100001101110xxxxxxxxxx", AInstEmit.Fcvtzs_V, typeof(AOpCodeSimd));
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Set("0x0011110>>xxxxx111111xxxxxxxxxx", AInstEmit.Fcvtzs_V, typeof(AOpCodeSimdShImm));
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Set("x0011110xx111001000000xxxxxxxxxx", AInstEmit.Fcvtzu_S, typeof(AOpCodeSimdCvt));
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Set("x0011110xx011001xxxxxxxxxxxxxxxx", AInstEmit.Fcvtzu_Fix, typeof(AOpCodeSimdCvt));
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Set("0x1011101x100001101110xxxxxxxxxx", AInstEmit.Fcvtzu_V, typeof(AOpCodeSimd));
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Set("0x1011110>>xxxxx111111xxxxxxxxxx", AInstEmit.Fcvtzu_V, typeof(AOpCodeSimdShImm));
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Set("00011110xx1xxxxx000110xxxxxxxxxx", AInstEmit.Fdiv_S, typeof(AOpCodeSimdReg));
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Set("00011111xx0xxxxx0xxxxxxxxxxxxxxx", AInstEmit.Fmadd_S, typeof(AOpCodeSimdReg));
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Set("00011110xx1xxxxx010010xxxxxxxxxx", AInstEmit.Fmax_S, typeof(AOpCodeSimdReg));
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@ -1,26 +1,16 @@
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using ChocolArm64.Instruction;
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using ChocolArm64.State;
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namespace ChocolArm64.Decoder
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{
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class AOpCodeSimdShImm : AOpCode, IAOpCodeSimd
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class AOpCodeSimdShImm : AOpCodeSimd
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{
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public int Rd { get; private set; }
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public int Rn { get; private set; }
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public int Imm { get; private set; }
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public int Size { get; private set; }
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public int Imm { get; private set; }
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public AOpCodeSimdShImm(AInst Inst, long Position, int OpCode) : base(Inst, Position)
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public AOpCodeSimdShImm(AInst Inst, long Position, int OpCode) : base(Inst, Position, OpCode)
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{
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Rd = (OpCode >> 0) & 0x1f;
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Rn = (OpCode >> 5) & 0x1f;
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Imm = (OpCode >> 16) & 0x7f;
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Size = ABitUtils.HighestBitSet32(Imm >> 3);
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RegisterSize = ((OpCode >> 30) & 1) != 0
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? ARegisterSize.SIMD128
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: ARegisterSize.SIMD64;
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}
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}
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}
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@ -102,80 +102,10 @@ namespace ChocolArm64.Instruction
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public static void Eor_V(AILEmitterCtx Context) => EmitVectorBinaryZx(Context, OpCodes.Xor);
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public static void Fadd_V(AILEmitterCtx Context)
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{
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AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp;
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public static void Fadd_V(AILEmitterCtx Context) => EmitVectorBinaryFOp(Context, OpCodes.Add);
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Context.EmitLdvec(Op.Rn);
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Context.EmitLdvec(Op.Rm);
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Context.EmitLdc_I4(Op.SizeF);
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ASoftFallback.EmitCall(Context,
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nameof(ASoftFallback.Fadd64),
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nameof(ASoftFallback.Fadd128));
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Context.EmitStvec(Op.Rd);
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}
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public static void Fcvtzs_V(AILEmitterCtx Context)
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{
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AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
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Context.EmitLdvec(Op.Rn);
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Context.EmitLdc_I4(0);
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Context.EmitLdc_I4(Op.SizeF);
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ASoftFallback.EmitCall(Context,
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nameof(ASoftFallback.Fcvtzs_V64),
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nameof(ASoftFallback.Fcvtzs_V128));
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Context.EmitStvec(Op.Rd);
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}
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public static void Fcvtzs_V_Fix(AILEmitterCtx Context)
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{
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AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp;
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Context.EmitLdvec(Op.Rn);
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Context.EmitLdc_I4((8 << (Op.Size + 1)) - Op.Imm);
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Context.EmitLdc_I4(Op.Size - 2);
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ASoftFallback.EmitCall(Context,
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nameof(ASoftFallback.Fcvtzs_V64),
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nameof(ASoftFallback.Fcvtzs_V128));
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Context.EmitStvec(Op.Rd);
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}
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public static void Fcvtzu_V(AILEmitterCtx Context)
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{
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AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
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Context.EmitLdvec(Op.Rn);
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Context.EmitLdc_I4(0);
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Context.EmitLdc_I4(Op.SizeF);
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ASoftFallback.EmitCall(Context,
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nameof(ASoftFallback.Fcvtzu_V_64),
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nameof(ASoftFallback.Fcvtzu_V_128));
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Context.EmitStvec(Op.Rd);
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}
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public static void Fcvtzu_V_Fix(AILEmitterCtx Context)
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{
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AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp;
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Context.EmitLdvec(Op.Rn);
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Context.EmitLdc_I4((8 << (Op.Size + 1)) - Op.Imm);
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Context.EmitLdc_I4(Op.Size - 2);
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ASoftFallback.EmitCall(Context,
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nameof(ASoftFallback.Fcvtzu_V_64),
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nameof(ASoftFallback.Fcvtzu_V_128));
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Context.EmitStvec(Op.Rd);
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}
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public static void Fcvtzs_V(AILEmitterCtx Context) => EmitVectorFcvtS(Context);
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public static void Fcvtzu_V(AILEmitterCtx Context) => EmitVectorFcvtU(Context);
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public static void Fmla_V(AILEmitterCtx Context)
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{
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@ -224,20 +154,7 @@ namespace ChocolArm64.Instruction
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Context.EmitStvec(Op.Rd);
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}
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public static void Fmul_V(AILEmitterCtx Context)
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{
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AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp;
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Context.EmitLdvec(Op.Rn);
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Context.EmitLdvec(Op.Rm);
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Context.EmitLdc_I4(Op.SizeF);
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ASoftFallback.EmitCall(Context,
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nameof(ASoftFallback.Fmul64),
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nameof(ASoftFallback.Fmul128));
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Context.EmitStvec(Op.Rd);
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}
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public static void Fmul_V(AILEmitterCtx Context) => EmitVectorBinaryFOp(Context, OpCodes.Mul);
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public static void Fmul_Vs(AILEmitterCtx Context)
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{
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@ -255,20 +172,7 @@ namespace ChocolArm64.Instruction
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Context.EmitStvec(Op.Rd);
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}
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public static void Fsub_V(AILEmitterCtx Context)
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{
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AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp;
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Context.EmitLdvec(Op.Rn);
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Context.EmitLdvec(Op.Rm);
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Context.EmitLdc_I4(Op.SizeF);
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ASoftFallback.EmitCall(Context,
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nameof(ASoftFallback.Fsub64),
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nameof(ASoftFallback.Fsub128));
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Context.EmitStvec(Op.Rd);
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}
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public static void Fsub_V(AILEmitterCtx Context) => EmitVectorBinaryFOp(Context, OpCodes.Sub);
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public static void Ins_Gp(AILEmitterCtx Context)
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{
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@ -870,6 +774,114 @@ namespace ChocolArm64.Instruction
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});
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}
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private static void EmitVectorFcvtS(AILEmitterCtx Context)
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{
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EmitVectorCvtOp(Context, CvtDir.Fcvt, true);
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}
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private static void EmitVectorFcvtU(AILEmitterCtx Context)
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{
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EmitVectorCvtOp(Context, CvtDir.Fcvt, false);
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}
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private static void EmitVectorCvtfS(AILEmitterCtx Context)
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{
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EmitVectorCvtOp(Context, CvtDir.Cvtf, true);
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}
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private static void EmitVectorCvtfU(AILEmitterCtx Context)
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{
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EmitVectorCvtOp(Context, CvtDir.Cvtf, false);
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}
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private enum CvtDir
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{
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Fcvt,
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Cvtf
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}
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private static void EmitVectorCvtOp(AILEmitterCtx Context, CvtDir Dir, bool Signed)
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{
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AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
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int SizeF = Op.Size & 1;
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int SizeI = SizeF + 2;
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int FBits = 0;
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if (Op is AOpCodeSimdShImm OpImm)
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{
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FBits = (8 << (Op.Size + 1)) - OpImm.Imm;
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}
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int Bytes = Context.CurrOp.GetBitsCount() >> 3;
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for (int Index = 0; Index < (Bytes >> SizeI); Index++)
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{
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EmitVectorExtractF(Context, Op.Rn, Index, SizeF);
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Context.EmitLdc_I4(FBits);
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if (Dir == CvtDir.Fcvt)
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{
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//Float to Integer.
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if (SizeF == 0)
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{
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ASoftFallback.EmitCall(Context, Signed
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? nameof(ASoftFallback.SatSingleToInt32)
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: nameof(ASoftFallback.SatSingleToUInt32));
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}
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else if (SizeF == 1)
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{
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ASoftFallback.EmitCall(Context, Signed
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? nameof(ASoftFallback.SatDoubleToInt64)
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: nameof(ASoftFallback.SatDoubleToUInt64));
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}
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}
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else if (Dir == CvtDir.Cvtf)
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{
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//Integer to Float.
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//TODO.
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}
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EmitVectorInsert(Context, Op.Rd, Index, SizeI);
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}
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if (Op.RegisterSize == ARegisterSize.SIMD64)
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{
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EmitVectorZeroUpper(Context, Op.Rd);
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}
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}
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private static void EmitVectorBinaryFOp(AILEmitterCtx Context, OpCode ILOp)
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{
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EmitVectorBinaryFOp(Context, () => Context.Emit(ILOp));
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}
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private static void EmitVectorBinaryFOp(AILEmitterCtx Context, Action Emit)
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{
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AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp;
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int SizeF = Op.Size & 1;
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int Bytes = Context.CurrOp.GetBitsCount() >> 3;
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for (int Index = 0; Index < (Bytes >> SizeF + 2); Index++)
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{
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EmitVectorExtractF(Context, Op.Rn, Index, SizeF);
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EmitVectorExtractF(Context, Op.Rm, Index, SizeF);
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Emit();
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EmitVectorInsertF(Context, Op.Rd, Index, SizeF);
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}
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if (Op.RegisterSize == ARegisterSize.SIMD64)
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{
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EmitVectorZeroUpper(Context, Op.Rd);
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}
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}
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private static void EmitVectorUnarySx(AILEmitterCtx Context, OpCode ILOp)
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{
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EmitVectorUnarySx(Context, () => Context.Emit(ILOp));
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@ -1047,6 +1059,25 @@ namespace ChocolArm64.Instruction
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}
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}
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private static void EmitVectorExtractF(AILEmitterCtx Context, int Reg, int Index, int Size)
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{
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Context.EmitLdvec(Reg);
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Context.EmitLdc_I4(Index);
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if (Size == 0)
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{
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ASoftFallback.EmitCall(Context, nameof(ASoftFallback.VectorExtractSingle));
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}
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else if (Size == 1)
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{
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ASoftFallback.EmitCall(Context, nameof(ASoftFallback.VectorExtractDouble));
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}
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else
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{
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throw new ArgumentOutOfRangeException(nameof(Size));
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}
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}
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private static void EmitVectorExtractSx(AILEmitterCtx Context, int Reg, int Index)
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{
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EmitVectorExtract(Context, Reg, Index, true);
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@ -1070,6 +1101,27 @@ namespace ChocolArm64.Instruction
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: nameof(ASoftFallback.ExtractVec));
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}
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private static void EmitVectorInsertF(AILEmitterCtx Context, int Reg, int Index, int Size)
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{
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Context.EmitLdvec(Reg);
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Context.EmitLdc_I4(Index);
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if (Size == 0)
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{
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ASoftFallback.EmitCall(Context, nameof(ASoftFallback.VectorInsertSingle));
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}
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else if (Size == 1)
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{
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ASoftFallback.EmitCall(Context, nameof(ASoftFallback.VectorInsertDouble));
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}
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else
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{
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throw new ArgumentOutOfRangeException(nameof(Size));
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}
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Context.EmitStvec(Reg);
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}
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private static void EmitVectorZeroLower(AILEmitterCtx Context, int Rd)
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{
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EmitVectorInsert(Context, Rd, 0, 3, 0);
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@ -1080,6 +1132,17 @@ namespace ChocolArm64.Instruction
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EmitVectorInsert(Context, Rd, 1, 3, 0);
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}
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private static void EmitVectorInsert(AILEmitterCtx Context, int Reg, int Index, int Size)
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{
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Context.EmitLdvec(Reg);
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Context.EmitLdc_I4(Index);
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Context.EmitLdc_I4(Size);
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ASoftFallback.EmitCall(Context, nameof(ASoftFallback.VectorInsertInt));
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Context.EmitStvec(Reg);
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}
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private static void EmitVectorInsert(AILEmitterCtx Context, int Reg, int Index, int Size, long Value)
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{
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Context.EmitLdvec(Reg);
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@ -365,122 +365,6 @@ namespace ChocolArm64.Instruction
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return Res;
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}
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public static AVec Fadd64(AVec LHS, AVec RHS, int Size)
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{
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return Fadd(LHS, RHS, Size, 2);
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}
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public static AVec Fadd128(AVec LHS, AVec RHS, int Size)
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{
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return Fadd(LHS, RHS, Size, 4);
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}
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private static AVec Fadd(AVec LHS, AVec RHS, int Size, int Bytes)
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{
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AVec Res = new AVec();
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int Elems = Bytes >> Size;
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if (Size == 0)
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{
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for (int Index = 0; Index < Elems; Index++)
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{
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float L = LHS.ExtractSingle(Index);
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float R = RHS.ExtractSingle(Index);
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Res = AVec.InsertSingle(Res, Index, L + R);
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}
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}
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else
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{
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for (int Index = 0; Index < Elems; Index++)
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{
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double L = LHS.ExtractDouble(Index);
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double R = RHS.ExtractDouble(Index);
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Res = AVec.InsertDouble(Res, Index, L + R);
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}
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}
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return Res;
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}
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public static AVec Fcvtzs_V64(AVec Vector, int FBits, int Size)
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{
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return Fcvtzs_V(Vector, FBits, Size, 2);
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}
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public static AVec Fcvtzs_V128(AVec Vector, int FBits, int Size)
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{
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return Fcvtzs_V(Vector, FBits, Size, 4);
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}
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private static AVec Fcvtzs_V(AVec Vector, int FBits, int Size, int Bytes)
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{
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AVec Res = new AVec();
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int Elems = Bytes >> Size;
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if (Size == 0)
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{
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for (int Index = 0; Index < Elems; Index++)
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{
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float Value = Vector.ExtractSingle(Index);
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Res = InsertSVec(Res, Index, Size + 2, SatSingleToInt32(Value, FBits));
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}
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}
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else
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{
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for (int Index = 0; Index < Elems; Index++)
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{
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double Value = Vector.ExtractDouble(Index);
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Res = InsertSVec(Res, Index, Size + 2, SatDoubleToInt64(Value, FBits));
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}
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}
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return Res;
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}
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public static AVec Fcvtzu_V_64(AVec Vector, int FBits, int Size)
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{
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return Fcvtzu_V(Vector, FBits, Size, 2);
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}
|
||||
|
||||
public static AVec Fcvtzu_V_128(AVec Vector, int FBits, int Size)
|
||||
{
|
||||
return Fcvtzu_V(Vector, FBits, Size, 4);
|
||||
}
|
||||
|
||||
private static AVec Fcvtzu_V(AVec Vector, int FBits, int Size, int Bytes)
|
||||
{
|
||||
AVec Res = new AVec();
|
||||
|
||||
int Elems = Bytes >> Size;
|
||||
|
||||
if (Size == 0)
|
||||
{
|
||||
for (int Index = 0; Index < Elems; Index++)
|
||||
{
|
||||
float Value = Vector.ExtractSingle(Index);
|
||||
|
||||
Res = InsertVec(Res, Index, Size + 2, SatSingleToUInt32(Value, FBits));
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
for (int Index = 0; Index < Elems; Index++)
|
||||
{
|
||||
double Value = Vector.ExtractDouble(Index);
|
||||
|
||||
Res = InsertVec(Res, Index, Size + 2, SatDoubleToUInt64(Value, FBits));
|
||||
}
|
||||
}
|
||||
|
||||
return Res;
|
||||
}
|
||||
|
||||
public static AVec Fmla64(AVec Res, AVec LHS, AVec RHS, int Size)
|
||||
{
|
||||
return Fmla(Res, LHS, RHS, Size, 2);
|
||||
|
|
@ -568,46 +452,6 @@ namespace ChocolArm64.Instruction
|
|||
return InsertVec(new AVec(), Elem, Size, Value);
|
||||
}
|
||||
|
||||
public static AVec Fmul64(AVec LHS, AVec RHS, int Size)
|
||||
{
|
||||
return Fmul(LHS, RHS, Size, 2);
|
||||
}
|
||||
|
||||
public static AVec Fmul128(AVec LHS, AVec RHS, int Size)
|
||||
{
|
||||
return Fmul(LHS, RHS, Size, 4);
|
||||
}
|
||||
|
||||
private static AVec Fmul(AVec LHS, AVec RHS, int Size, int Bytes)
|
||||
{
|
||||
AVec Res = new AVec();
|
||||
|
||||
int Elems = Bytes >> Size;
|
||||
|
||||
if (Size == 0)
|
||||
{
|
||||
for (int Index = 0; Index < Elems; Index++)
|
||||
{
|
||||
float L = LHS.ExtractSingle(Index);
|
||||
float R = RHS.ExtractSingle(Index);
|
||||
|
||||
Res = AVec.InsertSingle(Res, Index, L * R);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
for (int Index = 0; Index < Elems; Index++)
|
||||
{
|
||||
double L = LHS.ExtractDouble(Index);
|
||||
double R = RHS.ExtractDouble(Index);
|
||||
|
||||
Res = AVec.InsertDouble(Res, Index, L * R);
|
||||
}
|
||||
}
|
||||
|
||||
return Res;
|
||||
}
|
||||
|
||||
public static AVec Fmul_Ve64(AVec LHS, AVec RHS, int SIdx, int Size)
|
||||
{
|
||||
return Fmul_Ve(LHS, RHS, SIdx, Size, 2);
|
||||
|
|
@ -650,46 +494,6 @@ namespace ChocolArm64.Instruction
|
|||
return Res;
|
||||
}
|
||||
|
||||
public static AVec Fsub64(AVec LHS, AVec RHS, int Size)
|
||||
{
|
||||
return Fsub(LHS, RHS, Size, 2);
|
||||
}
|
||||
|
||||
public static AVec Fsub128(AVec LHS, AVec RHS, int Size)
|
||||
{
|
||||
return Fsub(LHS, RHS, Size, 4);
|
||||
}
|
||||
|
||||
private static AVec Fsub(AVec LHS, AVec RHS, int Size, int Bytes)
|
||||
{
|
||||
AVec Res = new AVec();
|
||||
|
||||
int Elems = Bytes >> Size;
|
||||
|
||||
if (Size == 0)
|
||||
{
|
||||
for (int Index = 0; Index < Elems; Index++)
|
||||
{
|
||||
float L = LHS.ExtractSingle(Index);
|
||||
float R = RHS.ExtractSingle(Index);
|
||||
|
||||
Res = AVec.InsertSingle(Res, Index, L - R);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
for (int Index = 0; Index < Elems; Index++)
|
||||
{
|
||||
double L = LHS.ExtractDouble(Index);
|
||||
double R = RHS.ExtractDouble(Index);
|
||||
|
||||
Res = AVec.InsertDouble(Res, Index, L - R);
|
||||
}
|
||||
}
|
||||
|
||||
return Res;
|
||||
}
|
||||
|
||||
public static AVec Ins_Gp(AVec Res, ulong Value, int Elem, int Size)
|
||||
{
|
||||
return InsertVec(Res, Elem, Size, Value);
|
||||
|
|
@ -1126,6 +930,39 @@ namespace ChocolArm64.Instruction
|
|||
throw new ArgumentOutOfRangeException(nameof(Size));
|
||||
}
|
||||
|
||||
public static float VectorExtractSingle(AVec Vector, int Index)
|
||||
{
|
||||
return Vector.ExtractSingle(Index);
|
||||
}
|
||||
|
||||
public static double VectorExtractDouble(AVec Vector, int Index)
|
||||
{
|
||||
return Vector.ExtractDouble(Index);
|
||||
}
|
||||
|
||||
public static AVec VectorInsertSingle(float Value, AVec Vector, int Index)
|
||||
{
|
||||
return AVec.InsertSingle(Vector, Index, Value);
|
||||
}
|
||||
|
||||
public static AVec VectorInsertDouble(double Value, AVec Vector, int Index)
|
||||
{
|
||||
return AVec.InsertDouble(Vector, Index, Value);
|
||||
}
|
||||
|
||||
public static AVec VectorInsertInt(ulong Value, AVec Vector, int Index, int Size)
|
||||
{
|
||||
switch (Size)
|
||||
{
|
||||
case 0: return AVec.InsertByte (Vector, Index, (byte)Value);
|
||||
case 1: return AVec.InsertUInt16(Vector, Index, (ushort)Value);
|
||||
case 2: return AVec.InsertUInt32(Vector, Index, (uint)Value);
|
||||
case 3: return AVec.InsertUInt64(Vector, Index, (ulong)Value);
|
||||
}
|
||||
|
||||
throw new ArgumentOutOfRangeException(nameof(Size));
|
||||
}
|
||||
|
||||
public static AVec InsertVec(AVec Vector, int Index, int Size, ulong Value)
|
||||
{
|
||||
switch (Size)
|
||||
|
|
|
|||
|
|
@ -1,5 +1,3 @@
|
|||
using ChocolArm64.Exceptions;
|
||||
using System;
|
||||
using System.Runtime.CompilerServices;
|
||||
|
||||
namespace ChocolArm64.Memory
|
||||
|
|
|
|||
|
|
@ -1,8 +1,6 @@
|
|||
using System;
|
||||
using System.Diagnostics;
|
||||
using System.IO;
|
||||
using System.Reflection;
|
||||
using System.Text;
|
||||
|
||||
namespace Ryujinx
|
||||
{
|
||||
|
|
|
|||
|
|
@ -1,15 +1,12 @@
|
|||
using ChocolArm64.Memory;
|
||||
using OpenTK.Audio;
|
||||
using OpenTK.Audio.OpenAL;
|
||||
using Ryujinx.OsHle.Handles;
|
||||
using Ryujinx.OsHle.Ipc;
|
||||
using static Ryujinx.OsHle.Objects.ObjHelper;
|
||||
|
||||
using System;
|
||||
using System.Collections.Generic;
|
||||
using System.IO;
|
||||
|
||||
using OpenTK.Audio;
|
||||
using OpenTK.Audio.OpenAL;
|
||||
|
||||
namespace Ryujinx.OsHle.Objects
|
||||
{
|
||||
class AudIAudioOut
|
||||
|
|
|
|||
Loading…
Reference in a new issue