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Add Fast Paths for Crypto instructions (A32/A64) (#1026)
* Add Fast Paths for Crypto instructions (A32/A64) * Replace additional XOR with passing in const zero.
This commit is contained in:
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a40d8d4a17
commit
f695a215ad
7 changed files with 122 additions and 8 deletions
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@ -74,6 +74,11 @@ namespace ARMeilleure.CodeGen.X86
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Add(X86Instruction.Addps, new InstructionInfo(BadOp, BadOp, BadOp, BadOp, 0x00000f58, InstructionFlags.Vex));
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Add(X86Instruction.Addsd, new InstructionInfo(BadOp, BadOp, BadOp, BadOp, 0x00000f58, InstructionFlags.Vex | InstructionFlags.PrefixF2));
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Add(X86Instruction.Addss, new InstructionInfo(BadOp, BadOp, BadOp, BadOp, 0x00000f58, InstructionFlags.Vex | InstructionFlags.PrefixF3));
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Add(X86Instruction.Aesdec, new InstructionInfo(BadOp, BadOp, BadOp, BadOp, 0x000f38de, InstructionFlags.Vex | InstructionFlags.Prefix66));
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Add(X86Instruction.Aesdeclast, new InstructionInfo(BadOp, BadOp, BadOp, BadOp, 0x000f38df, InstructionFlags.Vex | InstructionFlags.Prefix66));
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Add(X86Instruction.Aesenc, new InstructionInfo(BadOp, BadOp, BadOp, BadOp, 0x000f38dc, InstructionFlags.Vex | InstructionFlags.Prefix66));
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Add(X86Instruction.Aesenclast, new InstructionInfo(BadOp, BadOp, BadOp, BadOp, 0x000f38dd, InstructionFlags.Vex | InstructionFlags.Prefix66));
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Add(X86Instruction.Aesimc, new InstructionInfo(BadOp, BadOp, BadOp, BadOp, 0x000f38db, InstructionFlags.Vex | InstructionFlags.Prefix66));
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Add(X86Instruction.And, new InstructionInfo(0x00000021, 0x04000083, 0x04000081, BadOp, 0x00000023, InstructionFlags.None));
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Add(X86Instruction.Andnpd, new InstructionInfo(BadOp, BadOp, BadOp, BadOp, 0x00000f55, InstructionFlags.Vex | InstructionFlags.Prefix66));
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Add(X86Instruction.Andnps, new InstructionInfo(BadOp, BadOp, BadOp, BadOp, 0x00000f55, InstructionFlags.Vex));
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@ -17,6 +17,11 @@ namespace ARMeilleure.CodeGen.X86
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Add(Intrinsic.X86Addps, new IntrinsicInfo(X86Instruction.Addps, IntrinsicType.Binary));
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Add(Intrinsic.X86Addsd, new IntrinsicInfo(X86Instruction.Addsd, IntrinsicType.Binary));
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Add(Intrinsic.X86Addss, new IntrinsicInfo(X86Instruction.Addss, IntrinsicType.Binary));
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Add(Intrinsic.X86Aesdec, new IntrinsicInfo(X86Instruction.Aesdec, IntrinsicType.Binary));
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Add(Intrinsic.X86Aesdeclast, new IntrinsicInfo(X86Instruction.Aesdeclast, IntrinsicType.Binary));
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Add(Intrinsic.X86Aesenc, new IntrinsicInfo(X86Instruction.Aesenc, IntrinsicType.Binary));
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Add(Intrinsic.X86Aesenclast, new IntrinsicInfo(X86Instruction.Aesenclast, IntrinsicType.Binary));
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Add(Intrinsic.X86Aesimc, new IntrinsicInfo(X86Instruction.Aesimc, IntrinsicType.Unary));
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Add(Intrinsic.X86Andnpd, new IntrinsicInfo(X86Instruction.Andnpd, IntrinsicType.Binary));
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Add(Intrinsic.X86Andnps, new IntrinsicInfo(X86Instruction.Andnps, IntrinsicType.Binary));
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Add(Intrinsic.X86Andpd, new IntrinsicInfo(X86Instruction.Andpd, IntrinsicType.Binary));
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@ -7,6 +7,11 @@ namespace ARMeilleure.CodeGen.X86
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Addps,
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Addsd,
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Addss,
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Aesdec,
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Aesdeclast,
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Aesenc,
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Aesenclast,
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Aesimc,
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And,
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Andnpd,
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Andnps,
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@ -15,7 +15,17 @@ namespace ARMeilleure.Instructions
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Operand d = GetVec(op.Rd);
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Operand n = GetVec(op.Rn);
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context.Copy(d, context.Call(new _V128_V128_V128(SoftFallback.Decrypt), d, n));
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Operand res;
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if (Optimizations.UseAesni)
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{
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res = context.AddIntrinsic(Intrinsic.X86Aesdeclast, context.AddIntrinsic(Intrinsic.X86Xorpd, d, n), context.VectorZero());
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}
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else
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{
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res = context.Call(new _V128_V128_V128(SoftFallback.Decrypt), d, n);
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}
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context.Copy(d, res);
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}
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public static void Aese_V(ArmEmitterContext context)
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@ -25,7 +35,17 @@ namespace ARMeilleure.Instructions
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Operand d = GetVec(op.Rd);
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Operand n = GetVec(op.Rn);
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context.Copy(d, context.Call(new _V128_V128_V128(SoftFallback.Encrypt), d, n));
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Operand res;
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if (Optimizations.UseAesni)
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{
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res = context.AddIntrinsic(Intrinsic.X86Aesenclast, context.AddIntrinsic(Intrinsic.X86Xorpd, d, n), context.VectorZero());
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}
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else
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{
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res = context.Call(new _V128_V128_V128(SoftFallback.Encrypt), d, n);
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}
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context.Copy(d, res);
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}
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public static void Aesimc_V(ArmEmitterContext context)
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@ -34,7 +54,17 @@ namespace ARMeilleure.Instructions
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Operand n = GetVec(op.Rn);
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context.Copy(GetVec(op.Rd), context.Call(new _V128_V128(SoftFallback.InverseMixColumns), n));
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Operand res;
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if (Optimizations.UseAesni)
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{
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res = context.AddIntrinsic(Intrinsic.X86Aesimc, n);
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}
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else
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{
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res = context.Call(new _V128_V128(SoftFallback.InverseMixColumns), n);
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}
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context.Copy(GetVec(op.Rd), res);
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}
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public static void Aesmc_V(ArmEmitterContext context)
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@ -43,7 +73,23 @@ namespace ARMeilleure.Instructions
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Operand n = GetVec(op.Rn);
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context.Copy(GetVec(op.Rd), context.Call(new _V128_V128(SoftFallback.MixColumns), n));
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Operand res;
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if (Optimizations.UseAesni)
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{
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Operand roundKey = context.VectorZero();
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// Inverse Shift Rows, Inverse Sub Bytes, xor 0 so nothing happens
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res = context.AddIntrinsic(Intrinsic.X86Aesdeclast, n, roundKey);
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// Shift Rows, Sub Bytes, Mix Columns (!), xor 0 so nothing happens
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res = context.AddIntrinsic(Intrinsic.X86Aesenc, res, roundKey);
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}
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else
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{
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res = context.Call(new _V128_V128(SoftFallback.MixColumns), n);
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}
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context.Copy(GetVec(op.Rd), res);
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}
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}
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}
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@ -15,7 +15,17 @@ namespace ARMeilleure.Instructions
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Operand d = GetVecA32(op.Qd);
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Operand n = GetVecA32(op.Qm);
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context.Copy(d, context.Call(new _V128_V128_V128(SoftFallback.Decrypt), d, n));
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Operand res;
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if (Optimizations.UseAesni)
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{
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res = context.AddIntrinsic(Intrinsic.X86Aesdeclast, context.AddIntrinsic(Intrinsic.X86Xorpd, d, n), context.VectorZero());
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}
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else
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{
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res = context.Call(new _V128_V128_V128(SoftFallback.Decrypt), d, n);
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}
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context.Copy(d, res);
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}
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public static void Aese_V(ArmEmitterContext context)
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@ -25,7 +35,17 @@ namespace ARMeilleure.Instructions
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Operand d = GetVecA32(op.Qd);
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Operand n = GetVecA32(op.Qm);
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context.Copy(d, context.Call(new _V128_V128_V128(SoftFallback.Encrypt), d, n));
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Operand res;
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if (Optimizations.UseAesni)
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{
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res = context.AddIntrinsic(Intrinsic.X86Aesenclast, context.AddIntrinsic(Intrinsic.X86Xorpd, d, n), context.VectorZero());
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}
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else
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{
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res = context.Call(new _V128_V128_V128(SoftFallback.Encrypt), d, n);
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}
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context.Copy(d, res);
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}
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public static void Aesimc_V(ArmEmitterContext context)
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@ -34,7 +54,17 @@ namespace ARMeilleure.Instructions
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Operand n = GetVecA32(op.Qm);
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context.Copy(GetVec(op.Qd), context.Call(new _V128_V128(SoftFallback.InverseMixColumns), n));
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Operand res;
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if (Optimizations.UseAesni)
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{
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res = context.AddIntrinsic(Intrinsic.X86Aesimc, n);
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}
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else
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{
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res = context.Call(new _V128_V128(SoftFallback.InverseMixColumns), n);
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}
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context.Copy(GetVecA32(op.Qd), res);
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}
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public static void Aesmc_V(ArmEmitterContext context)
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@ -43,7 +73,23 @@ namespace ARMeilleure.Instructions
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Operand n = GetVecA32(op.Qm);
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context.Copy(GetVec(op.Qd), context.Call(new _V128_V128(SoftFallback.MixColumns), n));
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Operand res;
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if (Optimizations.UseAesni)
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{
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Operand roundKey = context.VectorZero();
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// Inverse Shift Rows, Inverse Sub Bytes, xor 0 so nothing happens.
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res = context.AddIntrinsic(Intrinsic.X86Aesdeclast, n, roundKey);
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// Shift Rows, Sub Bytes, Mix Columns (!), xor 0 so nothing happens.
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res = context.AddIntrinsic(Intrinsic.X86Aesenc, res, roundKey);
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}
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else
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{
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res = context.Call(new _V128_V128(SoftFallback.MixColumns), n);
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}
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context.Copy(GetVecA32(op.Qd), res);
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}
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}
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}
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@ -6,6 +6,11 @@ namespace ARMeilleure.IntermediateRepresentation
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X86Addps,
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X86Addsd,
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X86Addss,
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X86Aesdec,
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X86Aesdeclast,
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X86Aesenc,
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X86Aesenclast,
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X86Aesimc,
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X86Andnpd,
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X86Andnps,
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X86Andpd,
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@ -16,6 +16,7 @@ namespace ARMeilleure
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public static bool UseSse42IfAvailable { get; set; } = true;
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public static bool UsePopCntIfAvailable { get; set; } = true;
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public static bool UseAvxIfAvailable { get; set; } = true;
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public static bool UseAesniIfAvailable { get; set; } = true;
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public static bool ForceLegacySse
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{
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@ -31,5 +32,6 @@ namespace ARMeilleure
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internal static bool UseSse42 => UseSse42IfAvailable && HardwareCapabilities.SupportsSse42;
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internal static bool UsePopCnt => UsePopCntIfAvailable && HardwareCapabilities.SupportsPopcnt;
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internal static bool UseAvx => UseAvxIfAvailable && HardwareCapabilities.SupportsAvx && !ForceLegacySse;
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internal static bool UseAesni => UseAesniIfAvailable && HardwareCapabilities.SupportsAesni;
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}
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}
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