5 commits

Author	SHA1	Message	Date
gdkchan	161193e113	CPU refactoring - move SIMD (scalar and vector) instructions to separate files by category, remove AILConv and use only the methods inside SIMD helper to extract/insert vector elements	2018-02-17 18:06:11 -03:00
gdkchan	7c314eadcf	Emit CIL directly for more SIMD instructions, add UCVTF (vector, scalar) and UZP2, fix XTN (?)	2018-02-15 01:32:25 -03:00
gdkchan	b99e808791	Support loading NSO/NRO without a MOD0 header, stub some functions, support more ids on SvcGetInfo	2018-02-06 20:28:32 -03:00
gdkchan	2347c44bbf	Improve access to system registers by using properties, also use exclusive region granularity on exclusive load/stores, and ensure that acquires without releases won't hold the address forever, remove unused ALU rev method	2018-02-06 12:15:08 -03:00
gdkchan	b7e1d9930d	aloha	2018-02-04 20:08:20 -03:00