mirror of
https://github.com/ryujinx-mirror/ryujinx.git
synced 2024-12-24 02:05:46 +00:00
68e15c1a74
* Begin work on A32 SIMD Intrinsics * More instructions, some cleanup. * Intrinsics for Move instructions (zip etc) These pass the existing tests. * Intrinsics for some of Cvt While doing this I noticed that the conversion for int/fp was incorrect in the slow path. I'll fix this in the original repo. * Intrinsics for more Arithmetic instructions. * Intrinsics for Vext * Fix VEXT Intrinsic for double words. * Use InsertPs to move scalar values. * Cleanup, fix VPADD.f32 and VMIN signed integer. * Cleanup, add SSE2 support for scalar insert. Works similarly to the IR scalar insert, but obviously this one works directly on V128. * Minor cleanup. * Enable intrinsic for FP64 to integer conversion. * Address feedback apart from splitting out intrinsic float abs Also: bad VREV encodings as undefined rather than throwing in translation. * Move float abs to helper, fix bug with cvt * Rename opc2 & 3 to match A32 docs, use ArgumentOutOfRangeException appropriately. * Get name of variable at compilation rather than string literal. * Use correct double sign mask.
581 lines
22 KiB
C#
581 lines
22 KiB
C#
using ARMeilleure.Decoders;
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using ARMeilleure.IntermediateRepresentation;
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using ARMeilleure.State;
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using ARMeilleure.Translation;
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using System;
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using System.Diagnostics;
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using static ARMeilleure.Instructions.InstEmitHelper;
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using static ARMeilleure.Instructions.InstEmitSimdHelper;
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using static ARMeilleure.Instructions.InstEmitSimdHelper32;
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using static ARMeilleure.IntermediateRepresentation.OperandHelper;
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namespace ARMeilleure.Instructions
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{
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static partial class InstEmit32
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{
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private static int FlipVdBits(int vd, bool lowBit)
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{
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if (lowBit)
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{
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// Move the low bit to the top.
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return ((vd & 0x1) << 4) | (vd >> 1);
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}
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else
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{
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// Move the high bit to the bottom.
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return ((vd & 0xf) << 1) | (vd >> 4);
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}
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}
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private static Operand EmitSaturateFloatToInt(ArmEmitterContext context, Operand op1, bool unsigned)
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{
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if (op1.Type == OperandType.FP64)
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{
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if (unsigned)
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{
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return context.Call(new _U32_F64(SoftFallback.SatF64ToU32), op1);
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}
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else
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{
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return context.Call(new _S32_F64(SoftFallback.SatF64ToS32), op1);
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}
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}
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else
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{
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if (unsigned)
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{
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return context.Call(new _U32_F32(SoftFallback.SatF32ToU32), op1);
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}
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else
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{
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return context.Call(new _S32_F32(SoftFallback.SatF32ToS32), op1);
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}
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}
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}
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public static void Vcvt_V(ArmEmitterContext context)
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{
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OpCode32Simd op = (OpCode32Simd)context.CurrOp;
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bool unsigned = (op.Opc & 1) != 0;
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bool toInteger = (op.Opc & 2) != 0;
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OperandType floatSize = (op.Size == 2) ? OperandType.FP32 : OperandType.FP64;
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if (toInteger)
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{
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if (Optimizations.UseSse41)
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{
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EmitSse41ConvertVector32(context, FPRoundingMode.TowardsZero, !unsigned);
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}
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else
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{
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EmitVectorUnaryOpF32(context, (op1) =>
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{
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return EmitSaturateFloatToInt(context, op1, unsigned);
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});
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}
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}
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else
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{
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if (Optimizations.UseSse2)
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{
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EmitVectorUnaryOpSimd32(context, (n) =>
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{
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if (unsigned)
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{
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Operand mask = X86GetAllElements(context, 0x47800000);
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Operand res = context.AddIntrinsic(Intrinsic.X86Psrld, n, Const(16));
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res = context.AddIntrinsic(Intrinsic.X86Cvtdq2ps, res);
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res = context.AddIntrinsic(Intrinsic.X86Mulps, res, mask);
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Operand res2 = context.AddIntrinsic(Intrinsic.X86Pslld, n, Const(16));
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res2 = context.AddIntrinsic(Intrinsic.X86Psrld, res2, Const(16));
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res2 = context.AddIntrinsic(Intrinsic.X86Cvtdq2ps, res2);
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return context.AddIntrinsic(Intrinsic.X86Addps, res, res2);
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}
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else
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{
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return context.AddIntrinsic(Intrinsic.X86Cvtdq2ps, n);
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}
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});
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}
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else
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{
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if (unsigned)
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{
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EmitVectorUnaryOpZx32(context, (op1) => EmitFPConvert(context, op1, floatSize, false));
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}
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else
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{
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EmitVectorUnaryOpSx32(context, (op1) => EmitFPConvert(context, op1, floatSize, true));
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}
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}
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}
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}
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public static void Vcvt_FD(ArmEmitterContext context)
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{
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OpCode32SimdS op = (OpCode32SimdS)context.CurrOp;
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int vm = op.Vm;
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int vd;
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if (op.Size == 3)
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{
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vd = FlipVdBits(op.Vd, false);
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// Double to single.
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Operand fp = ExtractScalar(context, OperandType.FP64, vm);
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Operand res = context.ConvertToFP(OperandType.FP32, fp);
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InsertScalar(context, vd, res);
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}
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else
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{
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vd = FlipVdBits(op.Vd, true);
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// Single to double.
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Operand fp = ExtractScalar(context, OperandType.FP32, vm);
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Operand res = context.ConvertToFP(OperandType.FP64, fp);
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InsertScalar(context, vd, res);
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}
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}
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public static void Vcvt_FI(ArmEmitterContext context)
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{
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OpCode32SimdCvtFI op = (OpCode32SimdCvtFI)context.CurrOp;
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bool toInteger = (op.Opc2 & 0b100) != 0;
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OperandType floatSize = op.RegisterSize == RegisterSize.Int64 ? OperandType.FP64 : OperandType.FP32;
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if (toInteger)
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{
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bool unsigned = (op.Opc2 & 1) == 0;
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bool roundWithFpscr = op.Opc != 1;
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if (!roundWithFpscr && Optimizations.UseSse41)
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{
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EmitSse41ConvertInt32(context, FPRoundingMode.TowardsZero, !unsigned);
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}
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else
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{
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Operand toConvert = ExtractScalar(context, floatSize, op.Vm);
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Operand asInteger;
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// TODO: Fast Path.
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if (roundWithFpscr)
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{
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if (floatSize == OperandType.FP64)
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{
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if (unsigned)
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{
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asInteger = context.Call(new _U32_F64(SoftFallback.DoubleToUInt32), toConvert);
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}
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else
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{
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asInteger = context.Call(new _S32_F64(SoftFallback.DoubleToInt32), toConvert);
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}
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}
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else
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{
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if (unsigned)
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{
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asInteger = context.Call(new _U32_F32(SoftFallback.FloatToUInt32), toConvert);
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}
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else
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{
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asInteger = context.Call(new _S32_F32(SoftFallback.FloatToInt32), toConvert);
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}
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}
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}
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else
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{
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// Round towards zero.
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asInteger = EmitSaturateFloatToInt(context, toConvert, unsigned);
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}
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InsertScalar(context, op.Vd, asInteger);
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}
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}
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else
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{
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bool unsigned = op.Opc == 0;
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Operand toConvert = ExtractScalar(context, OperandType.I32, op.Vm);
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Operand asFloat = EmitFPConvert(context, toConvert, floatSize, !unsigned);
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InsertScalar(context, op.Vd, asFloat);
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}
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}
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public static Operand EmitRoundMathCall(ArmEmitterContext context, MidpointRounding roundMode, Operand n)
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{
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IOpCode32Simd op = (IOpCode32Simd)context.CurrOp;
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Delegate dlg;
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if ((op.Size & 1) == 0)
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{
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dlg = new _F32_F32_MidpointRounding(MathF.Round);
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}
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else /* if ((op.Size & 1) == 1) */
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{
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dlg = new _F64_F64_MidpointRounding(Math.Round);
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}
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return context.Call(dlg, n, Const((int)roundMode));
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}
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private static FPRoundingMode RMToRoundMode(int rm)
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{
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FPRoundingMode roundMode;
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switch (rm)
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{
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case 0b01:
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roundMode = FPRoundingMode.ToNearest;
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break;
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case 0b10:
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roundMode = FPRoundingMode.TowardsPlusInfinity;
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break;
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case 0b11:
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roundMode = FPRoundingMode.TowardsMinusInfinity;
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break;
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default:
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throw new ArgumentOutOfRangeException(nameof(rm));
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}
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return roundMode;
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}
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public static void Vcvt_R(ArmEmitterContext context)
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{
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OpCode32SimdCvtFI op = (OpCode32SimdCvtFI)context.CurrOp;
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OperandType floatSize = op.RegisterSize == RegisterSize.Int64 ? OperandType.FP64 : OperandType.FP32;
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bool unsigned = (op.Opc & 1) == 0;
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int rm = op.Opc2 & 3;
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if (Optimizations.UseSse41 && rm != 0b00)
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{
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EmitSse41ConvertInt32(context, RMToRoundMode(rm), !unsigned);
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}
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else
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{
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Operand toConvert = ExtractScalar(context, floatSize, op.Vm);
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switch (rm)
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{
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case 0b00: // Away
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toConvert = EmitRoundMathCall(context, MidpointRounding.AwayFromZero, toConvert);
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break;
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case 0b01: // Nearest
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toConvert = EmitRoundMathCall(context, MidpointRounding.ToEven, toConvert);
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break;
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case 0b10: // Towards positive infinity
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toConvert = EmitUnaryMathCall(context, MathF.Ceiling, Math.Ceiling, toConvert);
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break;
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case 0b11: // Towards negative infinity
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toConvert = EmitUnaryMathCall(context, MathF.Floor, Math.Floor, toConvert);
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break;
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}
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Operand asInteger;
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asInteger = EmitSaturateFloatToInt(context, toConvert, unsigned);
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InsertScalar(context, op.Vd, asInteger);
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}
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}
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public static void Vrint_RM(ArmEmitterContext context)
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{
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OpCode32SimdCvtFI op = (OpCode32SimdCvtFI)context.CurrOp;
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OperandType floatSize = op.RegisterSize == RegisterSize.Int64 ? OperandType.FP64 : OperandType.FP32;
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int rm = op.Opc2 & 3;
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if (Optimizations.UseSse2 && rm != 0b00)
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{
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EmitScalarUnaryOpSimd32(context, (m) =>
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{
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Intrinsic inst = (op.Size & 1) == 0 ? Intrinsic.X86Roundss : Intrinsic.X86Roundsd;
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FPRoundingMode roundMode = RMToRoundMode(rm);
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return context.AddIntrinsic(inst, m, Const(X86GetRoundControl(roundMode)));
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});
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}
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else
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{
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Operand toConvert = ExtractScalar(context, floatSize, op.Vm);
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switch (rm)
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{
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case 0b00: // Away
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toConvert = EmitRoundMathCall(context, MidpointRounding.AwayFromZero, toConvert);
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break;
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case 0b01: // Nearest
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toConvert = EmitRoundMathCall(context, MidpointRounding.ToEven, toConvert);
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break;
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case 0b10: // Towards positive infinity
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toConvert = EmitUnaryMathCall(context, MathF.Ceiling, Math.Ceiling, toConvert);
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break;
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case 0b11: // Towards negative infinity
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toConvert = EmitUnaryMathCall(context, MathF.Floor, Math.Floor, toConvert);
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break;
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}
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InsertScalar(context, op.Vd, toConvert);
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}
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}
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public static void Vrint_Z(ArmEmitterContext context)
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{
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IOpCodeSimd op = (IOpCodeSimd)context.CurrOp;
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if (Optimizations.UseSse2)
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{
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EmitScalarUnaryOpSimd32(context, (m) =>
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{
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Intrinsic inst = (op.Size & 1) == 0 ? Intrinsic.X86Roundss : Intrinsic.X86Roundsd;
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return context.AddIntrinsic(inst, m, Const(X86GetRoundControl(FPRoundingMode.TowardsZero)));
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});
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}
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else
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{
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EmitScalarUnaryOpF32(context, (op1) => EmitUnaryMathCall(context, MathF.Truncate, Math.Truncate, op1));
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}
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}
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private static Operand EmitFPConvert(ArmEmitterContext context, Operand value, OperandType type, bool signed)
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{
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Debug.Assert(value.Type == OperandType.I32 || value.Type == OperandType.I64);
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if (signed)
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{
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return context.ConvertToFP(type, value);
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}
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else
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{
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return context.ConvertToFPUI(type, value);
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}
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}
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private static void EmitSse41ConvertInt32(ArmEmitterContext context, FPRoundingMode roundMode, bool signed)
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{
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// A port of the similar round function in InstEmitSimdCvt.
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OpCode32SimdS op = (OpCode32SimdS)context.CurrOp;
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bool doubleSize = (op.Size & 1) != 0;
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int shift = doubleSize ? 1 : 2;
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Operand n = GetVecA32(op.Vm >> shift);
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n = EmitSwapScalar(context, n, op.Vm, doubleSize);
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if (!doubleSize)
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{
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Operand nRes = context.AddIntrinsic(Intrinsic.X86Cmpss, n, n, Const((int)CmpCondition.OrderedQ));
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nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n);
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nRes = context.AddIntrinsic(Intrinsic.X86Roundss, nRes, Const(X86GetRoundControl(roundMode)));
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Operand zero = context.VectorZero();
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Operand nCmp;
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Operand nIntOrLong2 = null;
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if (!signed)
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{
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nCmp = context.AddIntrinsic(Intrinsic.X86Cmpss, nRes, zero, Const((int)CmpCondition.NotLessThanOrEqual));
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nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp);
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}
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int fpMaxVal = 0x4F000000; // 2.14748365E9f (2147483648)
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Operand fpMaxValMask = X86GetScalar(context, fpMaxVal);
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Operand nIntOrLong = context.AddIntrinsicInt(Intrinsic.X86Cvtss2si, nRes);
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if (!signed)
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{
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nRes = context.AddIntrinsic(Intrinsic.X86Subss, nRes, fpMaxValMask);
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nCmp = context.AddIntrinsic(Intrinsic.X86Cmpss, nRes, zero, Const((int)CmpCondition.NotLessThanOrEqual));
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nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp);
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nIntOrLong2 = context.AddIntrinsicInt(Intrinsic.X86Cvtss2si, nRes);
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}
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nRes = context.AddIntrinsic(Intrinsic.X86Cmpss, nRes, fpMaxValMask, Const((int)CmpCondition.NotLessThan));
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Operand nInt = context.AddIntrinsicInt(Intrinsic.X86Cvtsi2si, nRes);
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Operand dRes;
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if (signed)
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{
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dRes = context.BitwiseExclusiveOr(nIntOrLong, nInt);
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}
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else
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{
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dRes = context.BitwiseExclusiveOr(nIntOrLong2, nInt);
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dRes = context.Add(dRes, nIntOrLong);
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}
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InsertScalar(context, op.Vd, dRes);
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}
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else
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{
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Operand nRes = context.AddIntrinsic(Intrinsic.X86Cmpsd, n, n, Const((int)CmpCondition.OrderedQ));
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nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n);
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nRes = context.AddIntrinsic(Intrinsic.X86Roundsd, nRes, Const(X86GetRoundControl(roundMode)));
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Operand zero = context.VectorZero();
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Operand nCmp;
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Operand nIntOrLong2 = null;
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if (!signed)
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{
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nCmp = context.AddIntrinsic(Intrinsic.X86Cmpsd, nRes, zero, Const((int)CmpCondition.NotLessThanOrEqual));
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nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp);
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}
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long fpMaxVal = 0x41E0000000000000L; // 2147483648.0000000d (2147483648)
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Operand fpMaxValMask = X86GetScalar(context, fpMaxVal);
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Operand nIntOrLong = context.AddIntrinsicInt(Intrinsic.X86Cvtsd2si, nRes);
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if (!signed)
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{
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nRes = context.AddIntrinsic(Intrinsic.X86Subsd, nRes, fpMaxValMask);
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nCmp = context.AddIntrinsic(Intrinsic.X86Cmpsd, nRes, zero, Const((int)CmpCondition.NotLessThanOrEqual));
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nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp);
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nIntOrLong2 = context.AddIntrinsicInt(Intrinsic.X86Cvtsd2si, nRes);
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}
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nRes = context.AddIntrinsic(Intrinsic.X86Cmpsd, nRes, fpMaxValMask, Const((int)CmpCondition.NotLessThan));
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Operand nLong = context.AddIntrinsicLong(Intrinsic.X86Cvtsi2si, nRes);
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nLong = context.ConvertI64ToI32(nLong);
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Operand dRes;
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if (signed)
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{
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dRes = context.BitwiseExclusiveOr(nIntOrLong, nLong);
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}
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else
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{
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dRes = context.BitwiseExclusiveOr(nIntOrLong2, nLong);
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dRes = context.Add(dRes, nIntOrLong);
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}
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InsertScalar(context, op.Vd, dRes);
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}
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}
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private static void EmitSse41ConvertVector32(ArmEmitterContext context, FPRoundingMode roundMode, bool signed)
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{
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OpCode32Simd op = (OpCode32Simd)context.CurrOp;
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EmitVectorUnaryOpSimd32(context, (n) =>
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{
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int sizeF = op.Size & 1;
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if (sizeF == 0)
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|
{
|
|
Operand nRes = context.AddIntrinsic(Intrinsic.X86Cmpps, n, n, Const((int)CmpCondition.OrderedQ));
|
|
nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n);
|
|
|
|
nRes = context.AddIntrinsic(Intrinsic.X86Roundps, nRes, Const(X86GetRoundControl(roundMode)));
|
|
|
|
Operand zero = context.VectorZero();
|
|
Operand nCmp;
|
|
if (!signed)
|
|
{
|
|
nCmp = context.AddIntrinsic(Intrinsic.X86Cmpps, nRes, zero, Const((int)CmpCondition.NotLessThanOrEqual));
|
|
nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp);
|
|
}
|
|
|
|
Operand fpMaxValMask = X86GetAllElements(context, 0x4F000000); // 2.14748365E9f (2147483648)
|
|
|
|
Operand nInt = context.AddIntrinsic(Intrinsic.X86Cvtps2dq, nRes);
|
|
Operand nInt2 = null;
|
|
if (!signed)
|
|
{
|
|
nRes = context.AddIntrinsic(Intrinsic.X86Subps, nRes, fpMaxValMask);
|
|
|
|
nCmp = context.AddIntrinsic(Intrinsic.X86Cmpps, nRes, zero, Const((int)CmpCondition.NotLessThanOrEqual));
|
|
nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp);
|
|
|
|
nInt2 = context.AddIntrinsic(Intrinsic.X86Cvtps2dq, nRes);
|
|
}
|
|
|
|
nRes = context.AddIntrinsic(Intrinsic.X86Cmpps, nRes, fpMaxValMask, Const((int)CmpCondition.NotLessThan));
|
|
|
|
if (signed)
|
|
{
|
|
return context.AddIntrinsic(Intrinsic.X86Pxor, nInt, nRes);
|
|
}
|
|
else
|
|
{
|
|
Operand dRes = context.AddIntrinsic(Intrinsic.X86Pxor, nInt2, nRes);
|
|
return context.AddIntrinsic(Intrinsic.X86Paddd, dRes, nInt);
|
|
}
|
|
}
|
|
else /* if (sizeF == 1) */
|
|
{
|
|
Operand nRes = context.AddIntrinsic(Intrinsic.X86Cmppd, n, n, Const((int)CmpCondition.OrderedQ));
|
|
nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n);
|
|
|
|
nRes = context.AddIntrinsic(Intrinsic.X86Roundpd, nRes, Const(X86GetRoundControl(roundMode)));
|
|
|
|
Operand zero = context.VectorZero();
|
|
Operand nCmp;
|
|
if (!signed)
|
|
{
|
|
nCmp = context.AddIntrinsic(Intrinsic.X86Cmppd, nRes, zero, Const((int)CmpCondition.NotLessThanOrEqual));
|
|
nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp);
|
|
}
|
|
|
|
Operand fpMaxValMask = X86GetAllElements(context, 0x43E0000000000000L); // 9.2233720368547760E18d (9223372036854775808)
|
|
|
|
Operand nLong = InstEmit.EmitSse2CvtDoubleToInt64OpF(context, nRes, false);
|
|
Operand nLong2 = null;
|
|
if (!signed)
|
|
{
|
|
nRes = context.AddIntrinsic(Intrinsic.X86Subpd, nRes, fpMaxValMask);
|
|
|
|
nCmp = context.AddIntrinsic(Intrinsic.X86Cmppd, nRes, zero, Const((int)CmpCondition.NotLessThanOrEqual));
|
|
nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp);
|
|
|
|
nLong2 = InstEmit.EmitSse2CvtDoubleToInt64OpF(context, nRes, false);
|
|
}
|
|
|
|
nRes = context.AddIntrinsic(Intrinsic.X86Cmppd, nRes, fpMaxValMask, Const((int)CmpCondition.NotLessThan));
|
|
|
|
if (signed)
|
|
{
|
|
return context.AddIntrinsic(Intrinsic.X86Pxor, nLong, nRes);
|
|
}
|
|
else
|
|
{
|
|
Operand dRes = context.AddIntrinsic(Intrinsic.X86Pxor, nLong2, nRes);
|
|
return context.AddIntrinsic(Intrinsic.X86Paddq, dRes, nLong);
|
|
}
|
|
}
|
|
});
|
|
}
|
|
}
|
|
}
|