emu-mirrors/ryujinx-fork
0
0
Fork 0
mirror of https://github.com/ryujinx-mirror/ryujinx.git synced 2024-12-24 00:05:45 +00:00
Code Activity
ryujinx-fork/ARMeilleure/State
History
LDj3SNuD 430ba6da65
CPU (A64): Add Pmull_V Inst. with Clmul fast path for the "1/2D -> 1Q" variant & Sse fast path and slow path for both the "8/16B -> 8H" and "1/2D -> 1Q" variants; with Test. (#1817) 
* Add Pmull_V Sse fast path only, both "8/16B -> 8H" and "1/2D -> 1Q" variants; with Test.

* Add Clmul fast path for the 128 bits variant.

* Small optimisation (save 60 instructions) for the Sse fast path about the 128 bits variant.

* Add slow path, both variants. Fix V128 Shl/Shr when shift = 0.

* A32: Add Vmull_I P64 variant (slow path); not tested.

* A32: Add Vmull_I_P8_P64 Test and fix P64 variant.
2021-01-04 23:45:54 +01:00
..
Aarch32Mode.cs Add a new JIT compiler for CPU code (#693) 2019-08-08 21:56:22 +03:00
ExecutionContext.cs IPC refactor part 2: Use ReplyAndReceive on HLE services and remove special handling from kernel (#1458) 2020-12-02 00:23:43 +01:00
ExecutionMode.cs PPTC Follow-up. (#1712) 2020-12-17 20:32:09 +01:00
FPCR.cs CPU: This PR fixes Fpscr, among other things. (#1433) 2020-08-08 17:18:51 +02:00
FPException.cs Add a new JIT compiler for CPU code (#693) 2019-08-08 21:56:22 +03:00
FPRoundingMode.cs Add a new JIT compiler for CPU code (#693) 2019-08-08 21:56:22 +03:00
FPSR.cs CPU: This PR fixes Fpscr, among other things. (#1433) 2020-08-08 17:18:51 +02:00
FPState.cs CPU: This PR fixes Fpscr, among other things. (#1433) 2020-08-08 17:18:51 +02:00
FPType.cs Add a new JIT compiler for CPU code (#693) 2019-08-08 21:56:22 +03:00
InstExceptionEventArgs.cs Add a new JIT compiler for CPU code (#693) 2019-08-08 21:56:22 +03:00
InstUndefinedEventArgs.cs Add a new JIT compiler for CPU code (#693) 2019-08-08 21:56:22 +03:00
NativeContext.cs Implement inline memory load/store exclusive and ordered (#1413) 2020-07-30 11:29:28 -03:00
PState.cs CPU: This PR fixes Fpscr, among other things. (#1433) 2020-08-08 17:18:51 +02:00
RegisterAlias.cs Add most of the A32 instruction set to ARMeilleure (#897) 2020-02-24 08:20:40 +11:00
RegisterConsts.cs Add most of the A32 instruction set to ARMeilleure (#897) 2020-02-24 08:20:40 +11:00
V128.cs CPU (A64): Add Pmull_V Inst. with Clmul fast path for the "1/2D -> 1Q" variant & Sse fast path and slow path for both the "8/16B -> 8H" and "1/2D -> 1Q" variants; with Test. (#1817) 2021-01-04 23:45:54 +01:00