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ryujinx-fork/Ryujinx/Cpu
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gdkchan 7d11a146c0 Generate CIL for SCVTF (vector), add undefined encodings for some instructions
2018-02-12 00:37:20 -03:00
..
Decoder Generate CIL for SCVTF (vector), add undefined encodings for some instructions 2018-02-12 00:37:20 -03:00
Exceptions Fixes to memory management 2018-02-09 21:13:18 -03:00
Instruction Generate CIL for SCVTF (vector), add undefined encodings for some instructions 2018-02-12 00:37:20 -03:00
Memory Fixes to memory management 2018-02-09 21:13:18 -03:00
State Generate CIL for SCVTF (vector), add undefined encodings for some instructions 2018-02-12 00:37:20 -03:00
Translation Support loading NSO/NRO without a MOD0 header, stub some functions, support more ids on SvcGetInfo 2018-02-06 20:28:32 -03:00
ABitUtils.cs aloha 2018-02-04 20:08:20 -03:00
AOpCodeTable.cs Generate CIL for SCVTF (vector), add undefined encodings for some instructions 2018-02-12 00:37:20 -03:00
AOptimizations.cs Add FVCTZS (fixed point variant) and LD1 (single structure variant) instructions 2018-02-09 00:26:20 -03:00
AThread.cs aloha 2018-02-04 20:08:20 -03:00
ATranslatedSub.cs aloha 2018-02-04 20:08:20 -03:00
ATranslator.cs aloha 2018-02-04 20:08:20 -03:00