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ryujinx-fork/Ryujinx.HLE/HOS/Services/Nv/NvGpuGpu/NvGpuGpuIoctl.cs
gdkchan a731ab3a2a Add a new JIT compiler for CPU code (#693)
* Start of the ARMeilleure project

* Refactoring around the old IRAdapter, now renamed to PreAllocator

* Optimize the LowestBitSet method

* Add CLZ support and fix CLS implementation

* Add missing Equals and GetHashCode overrides on some structs, misc small tweaks

* Implement the ByteSwap IR instruction, and some refactoring on the assembler

* Implement the DivideUI IR instruction and fix 64-bits IDIV

* Correct constant operand type on CSINC

* Move division instructions implementation to InstEmitDiv

* Fix destination type for the ConditionalSelect IR instruction

* Implement UMULH and SMULH, with new IR instructions

* Fix some issues with shift instructions

* Fix constant types for BFM instructions

* Fix up new tests using the new V128 struct

* Update tests

* Move DIV tests to a separate file

* Add support for calls, and some instructions that depends on them

* Start adding support for SIMD & FP types, along with some of the related ARM instructions

* Fix some typos and the divide instruction with FP operands

* Fix wrong method call on Clz_V

* Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes

* Implement SIMD logical instructions and more misc. fixes

* Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations

* Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes

* Implement SIMD shift instruction and fix Dup_V

* Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table

* Fix check with tolerance on tester

* Implement FP & SIMD comparison instructions, and some fixes

* Update FCVT (Scalar) encoding on the table to support the Half-float variants

* Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes

* Use old memory access methods, made a start on SIMD memory insts support, some fixes

* Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes

* Fix arguments count with struct return values, other fixes

* More instructions

* Misc. fixes and integrate LDj3SNuD fixes

* Update tests

* Add a faster linear scan allocator, unwinding support on windows, and other changes

* Update Ryujinx.HLE

* Update Ryujinx.Graphics

* Fix V128 return pointer passing, RCX is clobbered

* Update Ryujinx.Tests

* Update ITimeZoneService

* Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks

* Use generic GetFunctionPointerForDelegate method and other tweaks

* Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics

* Remove some unused code on the assembler

* Fix REX.W prefix regression on float conversion instructions, add some sort of profiler

* Add hardware capability detection

* Fix regression on Sha1h and revert Fcm** changes

* Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator

* Fix silly mistake introduced on last commit on CpuId

* Generate inline stack probes when the stack allocation is too large

* Initial support for the System-V ABI

* Support multiple destination operands

* Fix SSE2 VectorInsert8 path, and other fixes

* Change placement of XMM callee save and restore code to match other compilers

* Rename Dest to Destination and Inst to Instruction

* Fix a regression related to calls and the V128 type

* Add an extra space on comments to match code style

* Some refactoring

* Fix vector insert FP32 SSE2 path

* Port over the ARM32 instructions

* Avoid memory protection races on JIT Cache

* Another fix on VectorInsert FP32 (thanks to LDj3SNuD

* Float operands don't need to use the same register when VEX is supported

* Add a new register allocator, higher quality code for hot code (tier up), and other tweaks

* Some nits, small improvements on the pre allocator

* CpuThreadState is gone

* Allow changing CPU emulators with a config entry

* Add runtime identifiers on the ARMeilleure project

* Allow switching between CPUs through a config entry (pt. 2)

* Change win10-x64 to win-x64 on projects

* Update the Ryujinx project to use ARMeilleure

* Ensure that the selected register is valid on the hybrid allocator

* Allow exiting on returns to 0 (should fix test regression)

* Remove register assignments for most used variables on the hybrid allocator

* Do not use fixed registers as spill temp

* Add missing namespace and remove unneeded using

* Address PR feedback

* Fix types, etc

* Enable AssumeStrictAbiCompliance by default

* Ensure that Spill and Fill don't load or store any more than necessary
2019-08-08 21:56:22 +03:00

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6.4 KiB
C#

using ARMeilleure.Memory;
using Ryujinx.Common.Logging;
using System;
using System.Diagnostics;
namespace Ryujinx.HLE.HOS.Services.Nv.NvGpuGpu
{
class NvGpuGpuIoctl
{
private static Stopwatch _pTimer;
private static double _ticksToNs;
static NvGpuGpuIoctl()
{
_pTimer = new Stopwatch();
_pTimer.Start();
_ticksToNs = (1.0 / Stopwatch.Frequency) * 1_000_000_000;
}
public static int ProcessIoctl(ServiceCtx context, int cmd)
{
switch (cmd & 0xffff)
{
case 0x4701: return ZcullGetCtxSize (context);
case 0x4702: return ZcullGetInfo (context);
case 0x4703: return ZbcSetTable (context);
case 0x4705: return GetCharacteristics(context);
case 0x4706: return GetTpcMasks (context);
case 0x4714: return GetActiveSlotMask (context);
case 0x471c: return GetGpuTime (context);
}
throw new NotImplementedException(cmd.ToString("x8"));
}
private static int ZcullGetCtxSize(ServiceCtx context)
{
long outputPosition = context.Request.GetBufferType0x22().Position;
NvGpuGpuZcullGetCtxSize args = new NvGpuGpuZcullGetCtxSize();
args.Size = 1;
MemoryHelper.Write(context.Memory, outputPosition, args);
Logger.PrintStub(LogClass.ServiceNv);
return NvResult.Success;
}
private static int ZcullGetInfo(ServiceCtx context)
{
long outputPosition = context.Request.GetBufferType0x22().Position;
NvGpuGpuZcullGetInfo args = new NvGpuGpuZcullGetInfo();
args.WidthAlignPixels = 0x20;
args.HeightAlignPixels = 0x20;
args.PixelSquaresByAliquots = 0x400;
args.AliquotTotal = 0x800;
args.RegionByteMultiplier = 0x20;
args.RegionHeaderSize = 0x20;
args.SubregionHeaderSize = 0xc0;
args.SubregionWidthAlignPixels = 0x20;
args.SubregionHeightAlignPixels = 0x40;
args.SubregionCount = 0x10;
MemoryHelper.Write(context.Memory, outputPosition, args);
Logger.PrintStub(LogClass.ServiceNv);
return NvResult.Success;
}
private static int ZbcSetTable(ServiceCtx context)
{
long inputPosition = context.Request.GetBufferType0x21().Position;
long outputPosition = context.Request.GetBufferType0x22().Position;
Logger.PrintStub(LogClass.ServiceNv);
return NvResult.Success;
}
private static int GetCharacteristics(ServiceCtx context)
{
long inputPosition = context.Request.GetBufferType0x21().Position;
long outputPosition = context.Request.GetBufferType0x22().Position;
NvGpuGpuGetCharacteristics args = MemoryHelper.Read<NvGpuGpuGetCharacteristics>(context.Memory, inputPosition);
args.BufferSize = 0xa0;
args.Arch = 0x120;
args.Impl = 0xb;
args.Rev = 0xa1;
args.NumGpc = 0x1;
args.L2CacheSize = 0x40000;
args.OnBoardVideoMemorySize = 0x0;
args.NumTpcPerGpc = 0x2;
args.BusType = 0x20;
args.BigPageSize = 0x20000;
args.CompressionPageSize = 0x20000;
args.PdeCoverageBitCount = 0x1b;
args.AvailableBigPageSizes = 0x30000;
args.GpcMask = 0x1;
args.SmArchSmVersion = 0x503;
args.SmArchSpaVersion = 0x503;
args.SmArchWarpCount = 0x80;
args.GpuVaBitCount = 0x28;
args.Reserved = 0x0;
args.Flags = 0x55;
args.TwodClass = 0x902d;
args.ThreedClass = 0xb197;
args.ComputeClass = 0xb1c0;
args.GpfifoClass = 0xb06f;
args.InlineToMemoryClass = 0xa140;
args.DmaCopyClass = 0xb0b5;
args.MaxFbpsCount = 0x1;
args.FbpEnMask = 0x0;
args.MaxLtcPerFbp = 0x2;
args.MaxLtsPerLtc = 0x1;
args.MaxTexPerTpc = 0x0;
args.MaxGpcCount = 0x1;
args.RopL2EnMask0 = 0x21d70;
args.RopL2EnMask1 = 0x0;
args.ChipName = 0x6230326d67;
args.GrCompbitStoreBaseHw = 0x0;
MemoryHelper.Write(context.Memory, outputPosition, args);
return NvResult.Success;
}
private static int GetTpcMasks(ServiceCtx context)
{
long inputPosition = context.Request.GetBufferType0x21().Position;
long outputPosition = context.Request.GetBufferType0x22().Position;
NvGpuGpuGetTpcMasks args = MemoryHelper.Read<NvGpuGpuGetTpcMasks>(context.Memory, inputPosition);
if (args.MaskBufferSize != 0)
{
args.TpcMask = 3;
}
MemoryHelper.Write(context.Memory, outputPosition, args);
return NvResult.Success;
}
private static int GetActiveSlotMask(ServiceCtx context)
{
long outputPosition = context.Request.GetBufferType0x22().Position;
NvGpuGpuGetActiveSlotMask args = new NvGpuGpuGetActiveSlotMask();
args.Slot = 0x07;
args.Mask = 0x01;
MemoryHelper.Write(context.Memory, outputPosition, args);
Logger.PrintStub(LogClass.ServiceNv);
return NvResult.Success;
}
private static int GetGpuTime(ServiceCtx context)
{
long outputPosition = context.Request.GetBufferType0x22().Position;
context.Memory.WriteInt64(outputPosition, GetPTimerNanoSeconds());
return NvResult.Success;
}
private static long GetPTimerNanoSeconds()
{
double ticks = _pTimer.ElapsedTicks;
return (long)(ticks * _ticksToNs) & 0xff_ffff_ffff_ffff;
}
}
}