mirror of
https://github.com/ryujinx-mirror/ryujinx.git
synced 2024-12-24 18:05:45 +00:00
a731ab3a2a
* Start of the ARMeilleure project * Refactoring around the old IRAdapter, now renamed to PreAllocator * Optimize the LowestBitSet method * Add CLZ support and fix CLS implementation * Add missing Equals and GetHashCode overrides on some structs, misc small tweaks * Implement the ByteSwap IR instruction, and some refactoring on the assembler * Implement the DivideUI IR instruction and fix 64-bits IDIV * Correct constant operand type on CSINC * Move division instructions implementation to InstEmitDiv * Fix destination type for the ConditionalSelect IR instruction * Implement UMULH and SMULH, with new IR instructions * Fix some issues with shift instructions * Fix constant types for BFM instructions * Fix up new tests using the new V128 struct * Update tests * Move DIV tests to a separate file * Add support for calls, and some instructions that depends on them * Start adding support for SIMD & FP types, along with some of the related ARM instructions * Fix some typos and the divide instruction with FP operands * Fix wrong method call on Clz_V * Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes * Implement SIMD logical instructions and more misc. fixes * Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations * Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes * Implement SIMD shift instruction and fix Dup_V * Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table * Fix check with tolerance on tester * Implement FP & SIMD comparison instructions, and some fixes * Update FCVT (Scalar) encoding on the table to support the Half-float variants * Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes * Use old memory access methods, made a start on SIMD memory insts support, some fixes * Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes * Fix arguments count with struct return values, other fixes * More instructions * Misc. fixes and integrate LDj3SNuD fixes * Update tests * Add a faster linear scan allocator, unwinding support on windows, and other changes * Update Ryujinx.HLE * Update Ryujinx.Graphics * Fix V128 return pointer passing, RCX is clobbered * Update Ryujinx.Tests * Update ITimeZoneService * Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks * Use generic GetFunctionPointerForDelegate method and other tweaks * Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics * Remove some unused code on the assembler * Fix REX.W prefix regression on float conversion instructions, add some sort of profiler * Add hardware capability detection * Fix regression on Sha1h and revert Fcm** changes * Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator * Fix silly mistake introduced on last commit on CpuId * Generate inline stack probes when the stack allocation is too large * Initial support for the System-V ABI * Support multiple destination operands * Fix SSE2 VectorInsert8 path, and other fixes * Change placement of XMM callee save and restore code to match other compilers * Rename Dest to Destination and Inst to Instruction * Fix a regression related to calls and the V128 type * Add an extra space on comments to match code style * Some refactoring * Fix vector insert FP32 SSE2 path * Port over the ARM32 instructions * Avoid memory protection races on JIT Cache * Another fix on VectorInsert FP32 (thanks to LDj3SNuD * Float operands don't need to use the same register when VEX is supported * Add a new register allocator, higher quality code for hot code (tier up), and other tweaks * Some nits, small improvements on the pre allocator * CpuThreadState is gone * Allow changing CPU emulators with a config entry * Add runtime identifiers on the ARMeilleure project * Allow switching between CPUs through a config entry (pt. 2) * Change win10-x64 to win-x64 on projects * Update the Ryujinx project to use ARMeilleure * Ensure that the selected register is valid on the hybrid allocator * Allow exiting on returns to 0 (should fix test regression) * Remove register assignments for most used variables on the hybrid allocator * Do not use fixed registers as spill temp * Add missing namespace and remove unneeded using * Address PR feedback * Fix types, etc * Enable AssumeStrictAbiCompliance by default * Ensure that Spill and Fill don't load or store any more than necessary
362 lines
12 KiB
C#
362 lines
12 KiB
C#
#define Misc
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using ARMeilleure.State;
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using NUnit.Framework;
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namespace Ryujinx.Tests.Cpu
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{
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[Category("Misc")]
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public sealed class CpuTestMisc : CpuTest
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{
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#if Misc
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private const int RndCnt = 2;
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private const int RndCntImm = 2;
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#region "AluImm & Csel"
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[Test, Pairwise]
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public void Adds_Csinc_64bit([Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
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[Values(0u, 4095u)] [Random(0u, 4095u, RndCntImm)] uint imm,
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[Values(0b00u, 0b01u)] uint shift, // <LSL #0, LSL #12>
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[Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // <EQ, NE, CS/HS, CC/LO,
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0b0100u, 0b0101u, 0b0110u, 0b0111u, // MI, PL, VS, VC,
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0b1000u, 0b1001u, 0b1010u, 0b1011u, // HI, LS, GE, LT,
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0b1100u, 0b1101u)] uint cond) // GT, LE>
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{
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uint opCmn = 0xB100001F; // ADDS X31, X0, #0, LSL #0 -> CMN X0, #0, LSL #0
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uint opCset = 0x9A9F07E0; // CSINC X0, X31, X31, EQ -> CSET X0, NE
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opCmn |= ((shift & 3) << 22) | ((imm & 4095) << 10);
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opCset |= ((cond & 15) << 12);
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SetContext(x0: xn);
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Opcode(opCmn);
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Opcode(opCset);
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Opcode(0xD65F03C0); // RET
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ExecuteOpcodes();
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CompareAgainstUnicorn();
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}
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[Test, Pairwise]
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public void Adds_Csinc_32bit([Values(0x00000000u, 0x7FFFFFFFu,
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0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
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[Values(0u, 4095u)] [Random(0u, 4095u, RndCntImm)] uint imm,
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[Values(0b00u, 0b01u)] uint shift, // <LSL #0, LSL #12>
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[Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // <EQ, NE, CS/HS, CC/LO,
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0b0100u, 0b0101u, 0b0110u, 0b0111u, // MI, PL, VS, VC,
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0b1000u, 0b1001u, 0b1010u, 0b1011u, // HI, LS, GE, LT,
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0b1100u, 0b1101u)] uint cond) // GT, LE>
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{
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uint opCmn = 0x3100001F; // ADDS W31, W0, #0, LSL #0 -> CMN W0, #0, LSL #0
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uint opCset = 0x1A9F07E0; // CSINC W0, W31, W31, EQ -> CSET W0, NE
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opCmn |= ((shift & 3) << 22) | ((imm & 4095) << 10);
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opCset |= ((cond & 15) << 12);
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SetContext(x0: wn);
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Opcode(opCmn);
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Opcode(opCset);
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Opcode(0xD65F03C0); // RET
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ExecuteOpcodes();
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CompareAgainstUnicorn();
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}
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[Test, Pairwise]
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public void Subs_Csinc_64bit([Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
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[Values(0u, 4095u)] [Random(0u, 4095u, RndCntImm)] uint imm,
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[Values(0b00u, 0b01u)] uint shift, // <LSL #0, LSL #12>
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[Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // <EQ, NE, CS/HS, CC/LO,
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0b0100u, 0b0101u, 0b0110u, 0b0111u, // MI, PL, VS, VC,
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0b1000u, 0b1001u, 0b1010u, 0b1011u, // HI, LS, GE, LT,
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0b1100u, 0b1101u)] uint cond) // GT, LE>
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{
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uint opCmp = 0xF100001F; // SUBS X31, X0, #0, LSL #0 -> CMP X0, #0, LSL #0
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uint opCset = 0x9A9F07E0; // CSINC X0, X31, X31, EQ -> CSET X0, NE
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opCmp |= ((shift & 3) << 22) | ((imm & 4095) << 10);
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opCset |= ((cond & 15) << 12);
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SetContext(x0: xn);
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Opcode(opCmp);
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Opcode(opCset);
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Opcode(0xD65F03C0); // RET
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ExecuteOpcodes();
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CompareAgainstUnicorn();
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}
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[Test, Pairwise]
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public void Subs_Csinc_32bit([Values(0x00000000u, 0x7FFFFFFFu,
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0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
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[Values(0u, 4095u)] [Random(0u, 4095u, RndCntImm)] uint imm,
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[Values(0b00u, 0b01u)] uint shift, // <LSL #0, LSL #12>
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[Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // <EQ, NE, CS/HS, CC/LO,
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0b0100u, 0b0101u, 0b0110u, 0b0111u, // MI, PL, VS, VC,
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0b1000u, 0b1001u, 0b1010u, 0b1011u, // HI, LS, GE, LT,
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0b1100u, 0b1101u)] uint cond) // GT, LE>
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{
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uint opCmp = 0x7100001F; // SUBS W31, W0, #0, LSL #0 -> CMP W0, #0, LSL #0
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uint opCset = 0x1A9F07E0; // CSINC W0, W31, W31, EQ -> CSET W0, NE
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opCmp |= ((shift & 3) << 22) | ((imm & 4095) << 10);
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opCset |= ((cond & 15) << 12);
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SetContext(x0: wn);
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Opcode(opCmp);
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Opcode(opCset);
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Opcode(0xD65F03C0); // RET
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ExecuteOpcodes();
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CompareAgainstUnicorn();
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}
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#endregion
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[Explicit]
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[TestCase(0xFFFFFFFDu)] // Roots.
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[TestCase(0x00000005u)]
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public void Misc1(uint a)
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{
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// ((a + 3) * (a - 5)) / ((a + 5) * (a - 3)) = 0
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/*
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ADD W2, W0, 3
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SUB W1, W0, #5
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MUL W2, W2, W1
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ADD W1, W0, 5
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SUB W0, W0, #3
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MUL W0, W1, W0
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SDIV W0, W2, W0
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RET
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*/
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SetContext(x0: a);
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Opcode(0x11000C02);
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Opcode(0x51001401);
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Opcode(0x1B017C42);
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Opcode(0x11001401);
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Opcode(0x51000C00);
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Opcode(0x1B007C20);
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Opcode(0x1AC00C40);
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Opcode(0xD65F03C0);
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ExecuteOpcodes();
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Assert.That(GetContext().GetX(0), Is.Zero);
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}
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[Explicit]
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[TestCase(-20f, -5f)] // 18 integer solutions.
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[TestCase(-12f, -6f)]
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[TestCase(-12f, 3f)]
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[TestCase( -8f, -8f)]
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[TestCase( -6f, -12f)]
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[TestCase( -5f, -20f)]
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[TestCase( -4f, 2f)]
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[TestCase( -3f, 12f)]
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[TestCase( -2f, 4f)]
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[TestCase( 2f, -4f)]
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[TestCase( 3f, -12f)]
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[TestCase( 4f, -2f)]
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[TestCase( 5f, 20f)]
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[TestCase( 6f, 12f)]
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[TestCase( 8f, 8f)]
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[TestCase( 12f, -3f)]
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[TestCase( 12f, 6f)]
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[TestCase( 20f, 5f)]
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public void Misc2(float a, float b)
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{
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// 1 / ((1 / a + 1 / b) ^ 2) = 16
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/*
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FMOV S2, 1.0e+0
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FDIV S0, S2, S0
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FDIV S1, S2, S1
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FADD S0, S0, S1
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FDIV S0, S2, S0
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FMUL S0, S0, S0
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RET
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*/
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SetContext(v0: MakeVectorScalar(a), v1: MakeVectorScalar(b));
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Opcode(0x1E2E1002);
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Opcode(0x1E201840);
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Opcode(0x1E211841);
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Opcode(0x1E212800);
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Opcode(0x1E201840);
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Opcode(0x1E200800);
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Opcode(0xD65F03C0);
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ExecuteOpcodes();
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Assert.That(GetContext().GetV(0).AsFloat(), Is.EqualTo(16f));
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}
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[Explicit]
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[TestCase(-20d, -5d)] // 18 integer solutions.
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[TestCase(-12d, -6d)]
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[TestCase(-12d, 3d)]
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[TestCase( -8d, -8d)]
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[TestCase( -6d, -12d)]
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[TestCase( -5d, -20d)]
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[TestCase( -4d, 2d)]
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[TestCase( -3d, 12d)]
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[TestCase( -2d, 4d)]
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[TestCase( 2d, -4d)]
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[TestCase( 3d, -12d)]
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[TestCase( 4d, -2d)]
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[TestCase( 5d, 20d)]
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[TestCase( 6d, 12d)]
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[TestCase( 8d, 8d)]
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[TestCase( 12d, -3d)]
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[TestCase( 12d, 6d)]
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[TestCase( 20d, 5d)]
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public void Misc3(double a, double b)
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{
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// 1 / ((1 / a + 1 / b) ^ 2) = 16
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/*
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FMOV D2, 1.0e+0
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FDIV D0, D2, D0
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FDIV D1, D2, D1
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FADD D0, D0, D1
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FDIV D0, D2, D0
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FMUL D0, D0, D0
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RET
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*/
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SetContext(v0: MakeVectorScalar(a), v1: MakeVectorScalar(b));
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Opcode(0x1E6E1002);
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Opcode(0x1E601840);
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Opcode(0x1E611841);
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Opcode(0x1E612800);
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Opcode(0x1E601840);
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Opcode(0x1E600800);
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Opcode(0xD65F03C0);
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ExecuteOpcodes();
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Assert.That(GetContext().GetV(0).AsDouble(), Is.EqualTo(16d));
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}
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[Test, Ignore("The Tester supports only one return point.")]
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public void MiscF([Range(0u, 92u, 1u)] uint a)
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{
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ulong Fn(uint n)
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{
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ulong x = 0, y = 1, z;
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if (n == 0)
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{
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return x;
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}
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for (uint i = 2; i <= n; i++)
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{
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z = x + y;
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x = y;
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y = z;
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}
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return y;
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}
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/*
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0x0000000000001000: MOV W4, W0
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0x0000000000001004: CBZ W0, #0x34
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0x0000000000001008: CMP W0, #1
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0x000000000000100C: B.LS #0x34
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0x0000000000001010: MOVZ W2, #0x2
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0x0000000000001014: MOVZ X1, #0x1
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0x0000000000001018: MOVZ X3, #0
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0x000000000000101C: ADD X0, X3, X1
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0x0000000000001020: ADD W2, W2, #1
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0x0000000000001024: MOV X3, X1
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0x0000000000001028: MOV X1, X0
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0x000000000000102C: CMP W4, W2
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0x0000000000001030: B.HS #-0x14
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0x0000000000001034: RET
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0x0000000000001038: MOVZ X0, #0
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0x000000000000103C: RET
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0x0000000000001040: MOVZ X0, #0x1
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0x0000000000001044: RET
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*/
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SetContext(x0: a);
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Opcode(0x2A0003E4);
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Opcode(0x340001A0);
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Opcode(0x7100041F);
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Opcode(0x540001A9);
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Opcode(0x52800042);
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Opcode(0xD2800021);
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Opcode(0xD2800003);
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Opcode(0x8B010060);
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Opcode(0x11000442);
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Opcode(0xAA0103E3);
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Opcode(0xAA0003E1);
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Opcode(0x6B02009F);
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Opcode(0x54FFFF62);
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Opcode(0xD65F03C0);
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Opcode(0xD2800000);
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Opcode(0xD65F03C0);
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Opcode(0xD2800020);
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Opcode(0xD65F03C0);
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ExecuteOpcodes();
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Assert.That(GetContext().GetX(0), Is.EqualTo(Fn(a)));
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}
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[Explicit]
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[Test]
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public void MiscR()
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{
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const ulong result = 5;
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/*
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0x0000000000001000: MOV X0, #2
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0x0000000000001004: MOV X1, #3
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0x0000000000001008: ADD X0, X0, X1
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0x000000000000100C: RET
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*/
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Opcode(0xD2800040);
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Opcode(0xD2800061);
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Opcode(0x8B010000);
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Opcode(0xD65F03C0);
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ExecuteOpcodes();
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Assert.That(GetContext().GetX(0), Is.EqualTo(result));
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Reset();
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/*
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0x0000000000001000: MOV X0, #3
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0x0000000000001004: MOV X1, #2
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0x0000000000001008: ADD X0, X0, X1
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0x000000000000100C: RET
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*/
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Opcode(0xD2800060);
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Opcode(0xD2800041);
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Opcode(0x8B010000);
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Opcode(0xD65F03C0);
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ExecuteOpcodes();
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Assert.That(GetContext().GetX(0), Is.EqualTo(result));
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}
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[Explicit]
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[TestCase( 0ul)]
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[TestCase( 1ul)]
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[TestCase( 2ul)]
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[TestCase(42ul)]
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public void SanityCheck(ulong a)
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{
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uint opcode = 0xD503201F; // NOP
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ExecutionContext context = SingleOpcode(opcode, x0: a);
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Assert.That(context.GetX(0), Is.EqualTo(a));
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}
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#endif
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}
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}
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