mirror of
https://github.com/ryujinx-mirror/ryujinx.git
synced 2024-12-23 07:25:45 +00:00
c1bdf19061
* Implement ARM32 memory instructions: LDM, LDR, LDRB, LDRD, LDRH, LDRSB, LDRSH, STM, STR, STRB, STRD, STRH (immediate and register + immediate variants), implement CMP (immediate and register shifted by immediate variants) * Rename some opcode classes and flag masks for consistency * Fix a few suboptimal ARM32 codegen issues, only loads should be considered on decoder when checking if Rt == PC, and only NZCV flags should be considered for comparison optimizations * Take into account Rt2 for LDRD instructions aswell when checking if the instruction changes PC * Re-align arm32 instructions on the opcode table
29 lines
No EOL
697 B
C#
29 lines
No EOL
697 B
C#
using ChocolArm64.Instructions;
|
|
|
|
namespace ChocolArm64.Decoders
|
|
{
|
|
class OpCode32BImm : OpCode32, IOpCode32BImm
|
|
{
|
|
public long Imm { get; private set; }
|
|
|
|
public OpCode32BImm(Inst inst, long position, int opCode) : base(inst, position, opCode)
|
|
{
|
|
uint pc = GetPc();
|
|
|
|
//When the codition is never, the instruction is BLX to Thumb mode.
|
|
if (Cond != Condition.Nv)
|
|
{
|
|
pc &= ~3u;
|
|
}
|
|
|
|
Imm = pc + DecoderHelper.DecodeImm24_2(opCode);
|
|
|
|
if (Cond == Condition.Nv)
|
|
{
|
|
long H = (opCode >> 23) & 2;
|
|
|
|
Imm |= H;
|
|
}
|
|
}
|
|
}
|
|
} |