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https://github.com/ryujinx-mirror/ryujinx.git
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36e8e074c9
* Fix and simplify TranslatorCache * Fix some assignment alignments, remove some unused usings * Changes to ILEmitter, separate it from ILEmitterCtx * Rename ILEmitter to ILMethodBuilder * Rename LdrLit and *_Fix opcodes * Revert TranslatorCache impl to the more performant one, fix a few issues with it * Allow EmitOpCode to be called even after everything has been emitted * Make Emit and AdvanceOpCode private, simplify it a bit now that it starts emiting from the entry point * Remove unneeded temp use * Add missing exit call on TestExclusive * Use better hash * Implement the == and != operators
74 lines
No EOL
2.5 KiB
C#
74 lines
No EOL
2.5 KiB
C#
using System.Collections.Generic;
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namespace ChocolArm64.Translation
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{
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class ILBlock : IILEmit
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{
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public long IntInputs { get; private set; }
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public long IntOutputs { get; private set; }
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public long IntAwOutputs { get; private set; }
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public long VecInputs { get; private set; }
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public long VecOutputs { get; private set; }
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public long VecAwOutputs { get; private set; }
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public bool HasStateStore { get; private set; }
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private List<IILEmit> _emitters;
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public int Count => _emitters.Count;
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public ILBlock Next { get; set; }
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public ILBlock Branch { get; set; }
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public ILBlock()
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{
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_emitters = new List<IILEmit>();
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}
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public void Add(IILEmit emitter)
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{
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if (emitter is ILBarrier)
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{
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//Those barriers are used to separate the groups of CIL
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//opcodes emitted by each ARM instruction.
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//We can only consider the new outputs for doing input elimination
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//after all the CIL opcodes used by the instruction being emitted.
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IntAwOutputs = IntOutputs;
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VecAwOutputs = VecOutputs;
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}
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else if (emitter is ILOpCodeLoad ld && ILMethodBuilder.IsRegIndex(ld.Index))
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{
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switch (ld.IoType)
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{
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case IoType.Flag: IntInputs |= ((1L << ld.Index) << 32) & ~IntAwOutputs; break;
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case IoType.Int: IntInputs |= (1L << ld.Index) & ~IntAwOutputs; break;
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case IoType.Vector: VecInputs |= (1L << ld.Index) & ~VecAwOutputs; break;
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}
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}
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else if (emitter is ILOpCodeStore st && ILMethodBuilder.IsRegIndex(st.Index))
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{
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switch (st.IoType)
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{
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case IoType.Flag: IntOutputs |= (1L << st.Index) << 32; break;
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case IoType.Int: IntOutputs |= 1L << st.Index; break;
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case IoType.Vector: VecOutputs |= 1L << st.Index; break;
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}
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}
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else if (emitter is ILOpCodeStoreState)
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{
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HasStateStore = true;
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}
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_emitters.Add(emitter);
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}
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public void Emit(ILMethodBuilder context)
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{
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foreach (IILEmit ilEmitter in _emitters)
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{
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ilEmitter.Emit(context);
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}
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}
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}
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} |