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https://github.com/ryujinx-mirror/ryujinx.git
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f468db7602
* Implement Thumb (32-bit) memory (ordered), multiply and bitfield instructions * Remove public from interface * Fix T32 BL immediate and implement signed and unsigned extend instructions
237 lines
8.3 KiB
C#
237 lines
8.3 KiB
C#
using ARMeilleure.Decoders;
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using ARMeilleure.IntermediateRepresentation;
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using ARMeilleure.State;
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using ARMeilleure.Translation;
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using static ARMeilleure.Instructions.InstEmitHelper;
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using static ARMeilleure.Instructions.InstEmitMemoryExHelper;
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using static ARMeilleure.IntermediateRepresentation.Operand.Factory;
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namespace ARMeilleure.Instructions
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{
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static partial class InstEmit32
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{
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public static void Clrex(ArmEmitterContext context)
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{
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EmitClearExclusive(context);
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}
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public static void Csdb(ArmEmitterContext context)
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{
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// Execute as no-op.
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}
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public static void Dmb(ArmEmitterContext context) => EmitBarrier(context);
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public static void Dsb(ArmEmitterContext context) => EmitBarrier(context);
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public static void Ldrex(ArmEmitterContext context)
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{
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EmitExLoadOrStore(context, WordSizeLog2, AccessType.LoadZx | AccessType.Exclusive);
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}
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public static void Ldrexb(ArmEmitterContext context)
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{
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EmitExLoadOrStore(context, ByteSizeLog2, AccessType.LoadZx | AccessType.Exclusive);
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}
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public static void Ldrexd(ArmEmitterContext context)
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{
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EmitExLoadOrStore(context, DWordSizeLog2, AccessType.LoadZx | AccessType.Exclusive);
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}
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public static void Ldrexh(ArmEmitterContext context)
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{
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EmitExLoadOrStore(context, HWordSizeLog2, AccessType.LoadZx | AccessType.Exclusive);
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}
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public static void Lda(ArmEmitterContext context)
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{
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EmitExLoadOrStore(context, WordSizeLog2, AccessType.LoadZx | AccessType.Ordered);
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}
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public static void Ldab(ArmEmitterContext context)
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{
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EmitExLoadOrStore(context, ByteSizeLog2, AccessType.LoadZx | AccessType.Ordered);
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}
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public static void Ldaex(ArmEmitterContext context)
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{
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EmitExLoadOrStore(context, WordSizeLog2, AccessType.LoadZx | AccessType.Exclusive | AccessType.Ordered);
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}
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public static void Ldaexb(ArmEmitterContext context)
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{
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EmitExLoadOrStore(context, ByteSizeLog2, AccessType.LoadZx | AccessType.Exclusive | AccessType.Ordered);
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}
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public static void Ldaexd(ArmEmitterContext context)
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{
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EmitExLoadOrStore(context, DWordSizeLog2, AccessType.LoadZx | AccessType.Exclusive | AccessType.Ordered);
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}
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public static void Ldaexh(ArmEmitterContext context)
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{
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EmitExLoadOrStore(context, HWordSizeLog2, AccessType.LoadZx | AccessType.Exclusive | AccessType.Ordered);
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}
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public static void Ldah(ArmEmitterContext context)
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{
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EmitExLoadOrStore(context, HWordSizeLog2, AccessType.LoadZx | AccessType.Ordered);
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}
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// Stores.
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public static void Strex(ArmEmitterContext context)
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{
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EmitExLoadOrStore(context, WordSizeLog2, AccessType.Store | AccessType.Exclusive);
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}
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public static void Strexb(ArmEmitterContext context)
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{
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EmitExLoadOrStore(context, ByteSizeLog2, AccessType.Store | AccessType.Exclusive);
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}
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public static void Strexd(ArmEmitterContext context)
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{
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EmitExLoadOrStore(context, DWordSizeLog2, AccessType.Store | AccessType.Exclusive);
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}
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public static void Strexh(ArmEmitterContext context)
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{
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EmitExLoadOrStore(context, HWordSizeLog2, AccessType.Store | AccessType.Exclusive);
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}
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public static void Stl(ArmEmitterContext context)
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{
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EmitExLoadOrStore(context, WordSizeLog2, AccessType.Store | AccessType.Ordered);
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}
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public static void Stlb(ArmEmitterContext context)
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{
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EmitExLoadOrStore(context, ByteSizeLog2, AccessType.Store | AccessType.Ordered);
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}
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public static void Stlex(ArmEmitterContext context)
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{
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EmitExLoadOrStore(context, WordSizeLog2, AccessType.Store | AccessType.Exclusive | AccessType.Ordered);
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}
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public static void Stlexb(ArmEmitterContext context)
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{
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EmitExLoadOrStore(context, ByteSizeLog2, AccessType.Store | AccessType.Exclusive | AccessType.Ordered);
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}
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public static void Stlexd(ArmEmitterContext context)
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{
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EmitExLoadOrStore(context, DWordSizeLog2, AccessType.Store | AccessType.Exclusive | AccessType.Ordered);
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}
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public static void Stlexh(ArmEmitterContext context)
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{
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EmitExLoadOrStore(context, HWordSizeLog2, AccessType.Store | AccessType.Exclusive | AccessType.Ordered);
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}
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public static void Stlh(ArmEmitterContext context)
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{
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EmitExLoadOrStore(context, HWordSizeLog2, AccessType.Store | AccessType.Ordered);
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}
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private static void EmitExLoadOrStore(ArmEmitterContext context, int size, AccessType accType)
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{
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IOpCode32MemEx op = (IOpCode32MemEx)context.CurrOp;
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Operand address = context.Copy(GetIntA32(context, op.Rn));
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var exclusive = (accType & AccessType.Exclusive) != 0;
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var ordered = (accType & AccessType.Ordered) != 0;
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if ((accType & AccessType.Load) != 0)
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{
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if (ordered)
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{
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EmitBarrier(context);
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}
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if (size == DWordSizeLog2)
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{
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// Keep loads atomic - make the call to get the whole region and then decompose it into parts
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// for the registers.
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Operand value = EmitLoadExclusive(context, address, exclusive, size);
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Operand valueLow = context.ConvertI64ToI32(value);
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valueLow = context.ZeroExtend32(OperandType.I64, valueLow);
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Operand valueHigh = context.ShiftRightUI(value, Const(32));
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Operand lblBigEndian = Label();
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Operand lblEnd = Label();
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context.BranchIfTrue(lblBigEndian, GetFlag(PState.EFlag));
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SetIntA32(context, op.Rt, valueLow);
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SetIntA32(context, op.Rt2, valueHigh);
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context.Branch(lblEnd);
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context.MarkLabel(lblBigEndian);
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SetIntA32(context, op.Rt2, valueLow);
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SetIntA32(context, op.Rt, valueHigh);
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context.MarkLabel(lblEnd);
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}
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else
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{
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SetIntA32(context, op.Rt, EmitLoadExclusive(context, address, exclusive, size));
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}
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}
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else
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{
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if (size == DWordSizeLog2)
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{
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// Split the result into 2 words (based on endianness)
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Operand lo = context.ZeroExtend32(OperandType.I64, GetIntA32(context, op.Rt));
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Operand hi = context.ZeroExtend32(OperandType.I64, GetIntA32(context, op.Rt2));
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Operand lblBigEndian = Label();
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Operand lblEnd = Label();
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context.BranchIfTrue(lblBigEndian, GetFlag(PState.EFlag));
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Operand leResult = context.BitwiseOr(lo, context.ShiftLeft(hi, Const(32)));
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EmitStoreExclusive(context, address, leResult, exclusive, size, op.Rd, a32: true);
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context.Branch(lblEnd);
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context.MarkLabel(lblBigEndian);
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Operand beResult = context.BitwiseOr(hi, context.ShiftLeft(lo, Const(32)));
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EmitStoreExclusive(context, address, beResult, exclusive, size, op.Rd, a32: true);
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context.MarkLabel(lblEnd);
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}
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else
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{
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Operand value = context.ZeroExtend32(OperandType.I64, GetIntA32(context, op.Rt));
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EmitStoreExclusive(context, address, value, exclusive, size, op.Rd, a32: true);
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}
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if (ordered)
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{
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EmitBarrier(context);
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}
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}
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}
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private static void EmitBarrier(ArmEmitterContext context)
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{
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// Note: This barrier is most likely not necessary, and probably
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// doesn't make any difference since we need to do a ton of stuff
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// (software MMU emulation) to read or write anything anyway.
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}
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}
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}
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