mirror of
https://github.com/ryujinx-mirror/ryujinx.git
synced 2024-12-23 09:25:44 +00:00
1370 lines
No EOL
40 KiB
C#
1370 lines
No EOL
40 KiB
C#
using ChocolArm64.Decoder;
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using ChocolArm64.State;
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using ChocolArm64.Translation;
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using System;
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using System.Reflection;
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using System.Reflection.Emit;
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using static ChocolArm64.Instruction.AInstEmitMemoryHelper;
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namespace ChocolArm64.Instruction
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{
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static partial class AInstEmit
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{
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public static void Add_V(AILEmitterCtx Context)
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{
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EmitVectorBinaryZx(Context, () => Context.Emit(OpCodes.Add));
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}
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public static void Addp_V(AILEmitterCtx Context)
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{
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AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp;
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int Bytes = Context.CurrOp.GetBitsCount() >> 3;
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int Elems = Bytes >> Op.Size;
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int Half = Elems >> 1;
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for (int Index = 0; Index < Elems; Index++)
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{
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int Elem = (Index & (Half - 1)) << 1;
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EmitVectorExtractZx(Context, Index < Half ? Op.Rn : Op.Rm, Elem + 0, Op.Size);
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EmitVectorExtractZx(Context, Index < Half ? Op.Rn : Op.Rm, Elem + 1, Op.Size);
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Context.Emit(OpCodes.Add);
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EmitVectorInsert(Context, Op.Rd, Index, Op.Size);
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}
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if (Op.RegisterSize == ARegisterSize.SIMD64)
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{
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EmitVectorZeroUpper(Context, Op.Rd);
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}
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}
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public static void Addv_V(AILEmitterCtx Context)
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{
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AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
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int Bytes = Context.CurrOp.GetBitsCount() >> 3;
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int Results = 0;
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for (int Size = Op.Size; Size < 4; Size++)
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{
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for (int Index = 0; Index < (Bytes >> Size); Index += 2)
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{
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EmitVectorExtractZx(Context, Op.Rn, Index + 0, Size);
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EmitVectorExtractZx(Context, Op.Rn, Index + 1, Size);
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Context.Emit(OpCodes.Add);
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Results++;
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}
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}
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while (--Results > 0)
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{
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Context.Emit(OpCodes.Add);
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}
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EmitVectorZeroLower(Context, Op.Rd);
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EmitVectorZeroUpper(Context, Op.Rd);
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EmitVectorInsert(Context, Op.Rd, 0, Op.Size);
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}
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public static void And_V(AILEmitterCtx Context)
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{
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EmitVectorBinaryZx(Context, () => Context.Emit(OpCodes.And));
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}
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public static void Bic_V(AILEmitterCtx Context)
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{
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EmitVectorBinaryZx(Context, () =>
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{
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Context.Emit(OpCodes.Not);
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Context.Emit(OpCodes.And);
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});
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}
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public static void Bic_Vi(AILEmitterCtx Context)
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{
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EmitVectorImmBinary(Context, () =>
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{
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Context.Emit(OpCodes.Not);
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Context.Emit(OpCodes.And);
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});
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}
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public static void Bsl_V(AILEmitterCtx Context)
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{
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EmitVectorTernaryZx(Context, () =>
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{
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Context.EmitSttmp();
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Context.EmitLdtmp();
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Context.Emit(OpCodes.Xor);
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Context.Emit(OpCodes.And);
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Context.EmitLdtmp();
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Context.Emit(OpCodes.Xor);
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});
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}
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public static void Cmeq_V(AILEmitterCtx Context)
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{
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EmitVectorCmp(Context, OpCodes.Beq_S);
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}
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public static void Cmge_V(AILEmitterCtx Context)
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{
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EmitVectorCmp(Context, OpCodes.Bge_S);
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}
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public static void Cmgt_V(AILEmitterCtx Context)
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{
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EmitVectorCmp(Context, OpCodes.Bgt_S);
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}
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public static void Cmhi_V(AILEmitterCtx Context)
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{
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EmitVectorCmp(Context, OpCodes.Bgt_Un_S);
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}
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public static void Cmhs_V(AILEmitterCtx Context)
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{
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EmitVectorCmp(Context, OpCodes.Bge_Un_S);
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}
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public static void Cmle_V(AILEmitterCtx Context)
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{
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EmitVectorCmp(Context, OpCodes.Ble_S);
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}
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public static void Cmlt_V(AILEmitterCtx Context)
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{
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EmitVectorCmp(Context, OpCodes.Blt_S);
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}
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public static void Cnt_V(AILEmitterCtx Context)
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{
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AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
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int Elems = Op.RegisterSize == ARegisterSize.SIMD128 ? 16 : 8;
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for (int Index = 0; Index < Elems; Index++)
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{
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EmitVectorExtractZx(Context, Op.Rn, Index, 0);
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Context.Emit(OpCodes.Conv_U1);
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ASoftFallback.EmitCall(Context, nameof(ASoftFallback.CountSetBits8));
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Context.Emit(OpCodes.Conv_U8);
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EmitVectorInsert(Context, Op.Rd, Index, 0);
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}
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}
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public static void Dup_Gp(AILEmitterCtx Context)
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{
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AOpCodeSimdIns Op = (AOpCodeSimdIns)Context.CurrOp;
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int Bytes = Context.CurrOp.GetBitsCount() >> 3;
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for (int Index = 0; Index < (Bytes >> Op.Size); Index++)
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{
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Context.EmitLdintzr(Op.Rn);
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EmitVectorInsert(Context, Op.Rd, Index, Op.Size);
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}
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if (Op.RegisterSize == ARegisterSize.SIMD64)
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{
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EmitVectorZeroUpper(Context, Op.Rd);
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}
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}
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public static void Dup_V(AILEmitterCtx Context)
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{
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AOpCodeSimdIns Op = (AOpCodeSimdIns)Context.CurrOp;
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int Bytes = Context.CurrOp.GetBitsCount() >> 3;
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for (int Index = 0; Index < (Bytes >> Op.Size); Index++)
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{
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EmitVectorExtractZx(Context, Op.Rn, Op.DstIndex, Op.Size);
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EmitVectorInsert(Context, Op.Rd, Index, Op.Size);
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}
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if (Op.RegisterSize == ARegisterSize.SIMD64)
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{
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EmitVectorZeroUpper(Context, Op.Rd);
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}
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}
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public static void Eor_V(AILEmitterCtx Context)
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{
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EmitVectorBinaryZx(Context, () => Context.Emit(OpCodes.Xor));
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}
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public static void Fadd_V(AILEmitterCtx Context)
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{
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EmitVectorBinaryF(Context, () => Context.Emit(OpCodes.Add));
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}
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public static void Fcvtzs_V(AILEmitterCtx Context)
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{
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EmitVectorFcvt(Context, Signed: true);
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}
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public static void Fcvtzu_V(AILEmitterCtx Context)
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{
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EmitVectorFcvt(Context, Signed: false);
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}
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public static void Fmla_V(AILEmitterCtx Context)
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{
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AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp;
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EmitVectorTernaryF(Context, () =>
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{
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Context.Emit(OpCodes.Mul);
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Context.Emit(OpCodes.Add);
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});
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}
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public static void Fmla_Ve(AILEmitterCtx Context)
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{
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EmitVectorTernaryByElemF(Context, () =>
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{
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Context.Emit(OpCodes.Mul);
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Context.Emit(OpCodes.Add);
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});
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}
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public static void Fmov_V(AILEmitterCtx Context)
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{
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AOpCodeSimdImm Op = (AOpCodeSimdImm)Context.CurrOp;
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Context.EmitLdc_I8(Op.Imm);
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Context.EmitLdc_I4(Op.Size + 2);
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ASoftFallback.EmitCall(Context,
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nameof(ASoftFallback.Dup_Gp64),
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nameof(ASoftFallback.Dup_Gp128));
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Context.EmitStvec(Op.Rd);
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}
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public static void Fmul_V(AILEmitterCtx Context)
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{
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EmitVectorBinaryF(Context, () => Context.Emit(OpCodes.Mul));
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}
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public static void Fmul_Ve(AILEmitterCtx Context)
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{
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EmitVectorBinaryByElemF(Context, () => Context.Emit(OpCodes.Mul));
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}
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public static void Fsub_V(AILEmitterCtx Context)
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{
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EmitVectorBinaryF(Context, () => Context.Emit(OpCodes.Sub));
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}
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public static void Ins_Gp(AILEmitterCtx Context)
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{
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AOpCodeSimdIns Op = (AOpCodeSimdIns)Context.CurrOp;
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Context.EmitLdintzr(Op.Rn);
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EmitVectorInsert(Context, Op.Rd, Op.DstIndex, Op.Size);
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}
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public static void Ins_V(AILEmitterCtx Context)
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{
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AOpCodeSimdIns Op = (AOpCodeSimdIns)Context.CurrOp;
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EmitVectorExtractZx(Context, Op.Rn, Op.SrcIndex, Op.Size);
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EmitVectorInsert(Context, Op.Rd, Op.DstIndex, Op.Size);
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}
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public static void Ld__Vms(AILEmitterCtx Context)
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{
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EmitSimdMemMs(Context, IsLoad: true);
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}
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public static void Ld__Vss(AILEmitterCtx Context)
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{
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EmitSimdMemSs(Context, IsLoad: true);
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}
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public static void Mla_V(AILEmitterCtx Context)
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{
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EmitVectorTernaryZx(Context, () =>
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{
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Context.Emit(OpCodes.Mul);
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Context.Emit(OpCodes.Add);
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});
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}
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public static void Movi_V(AILEmitterCtx Context)
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{
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EmitVectorImmUnary(Context, () => { });
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}
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public static void Mul_V(AILEmitterCtx Context)
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{
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EmitVectorBinaryZx(Context, () => Context.Emit(OpCodes.Mul));
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}
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public static void Mvni_V(AILEmitterCtx Context)
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{
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EmitVectorImmUnary(Context, () => Context.Emit(OpCodes.Not));
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}
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public static void Neg_V(AILEmitterCtx Context)
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{
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EmitVectorUnarySx(Context, () => Context.Emit(OpCodes.Neg));
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}
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public static void Not_V(AILEmitterCtx Context)
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{
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EmitVectorUnaryZx(Context, () => Context.Emit(OpCodes.Not));
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}
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public static void Orr_V(AILEmitterCtx Context)
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{
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EmitVectorBinaryZx(Context, () => Context.Emit(OpCodes.Or));
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}
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public static void Orr_Vi(AILEmitterCtx Context)
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{
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EmitVectorImmBinary(Context, () => Context.Emit(OpCodes.Or));
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}
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public static void Saddw_V(AILEmitterCtx Context)
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{
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EmitVectorWidenBinarySx(Context, () => Context.Emit(OpCodes.Add));
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}
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public static void Scvtf_V(AILEmitterCtx Context)
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{
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EmitVectorCvtf(Context, Signed: true);
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}
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public static void Shl_V(AILEmitterCtx Context)
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{
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AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp;
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int Shift = Op.Imm - (8 << Op.Size);
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EmitVectorShImmBinaryZx(Context, () => Context.Emit(OpCodes.Shl), Shift);
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}
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public static void Shrn_V(AILEmitterCtx Context)
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{
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AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp;
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int Shift = (8 << (Op.Size + 1)) - Op.Imm;
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EmitVectorShImmNarrowBinaryZx(Context, () => Context.Emit(OpCodes.Shr_Un), Shift);
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}
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public static void Smax_V(AILEmitterCtx Context)
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{
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Type[] Types = new Type[] { typeof(long), typeof(long) };
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MethodInfo MthdInfo = typeof(Math).GetMethod(nameof(Math.Max), Types);
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EmitVectorBinarySx(Context, () => Context.EmitCall(MthdInfo));
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}
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public static void Smin_V(AILEmitterCtx Context)
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{
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Type[] Types = new Type[] { typeof(long), typeof(long) };
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MethodInfo MthdInfo = typeof(Math).GetMethod(nameof(Math.Min), Types);
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EmitVectorBinarySx(Context, () => Context.EmitCall(MthdInfo));
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}
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public static void Sshl_V(AILEmitterCtx Context)
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{
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EmitVectorShl(Context, Signed: true);
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}
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public static void Sshll_V(AILEmitterCtx Context)
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{
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AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp;
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int Shift = Op.Imm - (8 << Op.Size);
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EmitVectorShImmWidenBinarySx(Context, () => Context.Emit(OpCodes.Shl), Shift);
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}
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public static void Sshr_V(AILEmitterCtx Context)
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{
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AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp;
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int Shift = (8 << (Op.Size + 1)) - Op.Imm;
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EmitVectorShImmBinarySx(Context, () => Context.Emit(OpCodes.Shr), Shift);
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}
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public static void St__Vms(AILEmitterCtx Context)
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{
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EmitSimdMemMs(Context, IsLoad: false);
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}
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public static void St__Vss(AILEmitterCtx Context)
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{
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EmitSimdMemSs(Context, IsLoad: false);
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}
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public static void Sub_V(AILEmitterCtx Context)
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{
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EmitVectorBinaryZx(Context, () => Context.Emit(OpCodes.Sub));
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}
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public static void Tbl_V(AILEmitterCtx Context)
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{
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AOpCodeSimdTbl Op = (AOpCodeSimdTbl)Context.CurrOp;
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Context.EmitLdvec(Op.Rm);
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for (int Index = 0; Index < Op.Size; Index++)
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{
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Context.EmitLdvec((Op.Rn + Index) & 0x1f);
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}
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switch (Op.Size)
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{
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case 1: ASoftFallback.EmitCall(Context,
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nameof(ASoftFallback.Tbl1_V64),
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nameof(ASoftFallback.Tbl1_V128)); break;
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case 2: ASoftFallback.EmitCall(Context,
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nameof(ASoftFallback.Tbl2_V64),
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nameof(ASoftFallback.Tbl2_V128)); break;
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case 3: ASoftFallback.EmitCall(Context,
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nameof(ASoftFallback.Tbl3_V64),
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nameof(ASoftFallback.Tbl3_V128)); break;
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case 4: ASoftFallback.EmitCall(Context,
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nameof(ASoftFallback.Tbl4_V64),
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nameof(ASoftFallback.Tbl4_V128)); break;
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default: throw new InvalidOperationException();
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}
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Context.EmitStvec(Op.Rd);
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}
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public static void Uaddlv_V(AILEmitterCtx Context)
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{
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AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
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int Bytes = Context.CurrOp.GetBitsCount() >> 3;
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EmitVectorExtractZx(Context, Op.Rn, 0, Op.Size);
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for (int Index = 1; Index < (Bytes >> Op.Size); Index++)
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{
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EmitVectorExtractZx(Context, Op.Rn, Index, Op.Size);
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Context.Emit(OpCodes.Add);
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}
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EmitVectorZeroLower(Context, Op.Rd);
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EmitVectorZeroUpper(Context, Op.Rd);
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EmitVectorInsert(Context, Op.Rd, 0, Op.Size);
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}
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public static void Uaddw_V(AILEmitterCtx Context)
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{
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EmitVectorWidenBinaryZx(Context, () => Context.Emit(OpCodes.Add));
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}
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public static void Ucvtf_V(AILEmitterCtx Context)
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{
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EmitVectorCvtf(Context, Signed: false);
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}
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public static void Ushl_V(AILEmitterCtx Context)
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{
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EmitVectorShl(Context, Signed: false);
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}
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public static void Ushll_V(AILEmitterCtx Context)
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{
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AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp;
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int Shift = Op.Imm - (8 << Op.Size);
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EmitVectorShImmWidenBinaryZx(Context, () => Context.Emit(OpCodes.Shl), Shift);
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}
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public static void Ushr_V(AILEmitterCtx Context)
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{
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EmitVectorShr(Context, ShrFlags.None);
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}
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public static void Usra_V(AILEmitterCtx Context)
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{
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EmitVectorShr(Context, ShrFlags.Accumulate);
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}
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[Flags]
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private enum ShrFlags
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{
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None = 0,
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Signed = 1 << 0,
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Rounding = 1 << 1,
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Accumulate = 1 << 2
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}
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private static void EmitVectorShr(AILEmitterCtx Context, ShrFlags Flags)
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{
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AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp;
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|
|
int Shift = (8 << (Op.Size + 1)) - Op.Imm;
|
|
|
|
if (Flags.HasFlag(ShrFlags.Accumulate))
|
|
{
|
|
Action Emit = () =>
|
|
{
|
|
Context.EmitLdc_I4(Shift);
|
|
|
|
Context.Emit(OpCodes.Shr_Un);
|
|
Context.Emit(OpCodes.Add);
|
|
};
|
|
|
|
EmitVectorOp(Context, Emit, OperFlags.RdRn, Signed: false);
|
|
}
|
|
else
|
|
{
|
|
EmitVectorUnaryZx(Context, () =>
|
|
{
|
|
Context.EmitLdc_I4(Shift);
|
|
|
|
Context.Emit(OpCodes.Shr_Un);
|
|
});
|
|
}
|
|
}
|
|
|
|
public static void Uzp1_V(AILEmitterCtx Context)
|
|
{
|
|
EmitVectorUnzip(Context, Part: 0);
|
|
}
|
|
|
|
public static void Uzp2_V(AILEmitterCtx Context)
|
|
{
|
|
EmitVectorUnzip(Context, Part: 1);
|
|
}
|
|
|
|
private static void EmitVectorUnzip(AILEmitterCtx Context, int Part)
|
|
{
|
|
AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp;
|
|
|
|
int Bytes = Context.CurrOp.GetBitsCount() >> 3;
|
|
|
|
int Elems = Bytes >> Op.Size;
|
|
int Half = Elems >> 1;
|
|
|
|
for (int Index = 0; Index < Elems; Index++)
|
|
{
|
|
int Elem = Part + ((Index & (Half - 1)) << 1);
|
|
|
|
EmitVectorExtractZx(Context, Index < Half ? Op.Rn : Op.Rm, Elem, Op.Size);
|
|
|
|
EmitVectorInsert(Context, Op.Rd, Index, Op.Size);
|
|
}
|
|
|
|
if (Op.RegisterSize == ARegisterSize.SIMD64)
|
|
{
|
|
EmitVectorZeroUpper(Context, Op.Rd);
|
|
}
|
|
}
|
|
|
|
public static void Xtn_V(AILEmitterCtx Context)
|
|
{
|
|
AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
|
|
|
|
int Elems = 8 >> Op.Size;
|
|
|
|
int Part = Op.RegisterSize == ARegisterSize.SIMD128 ? Elems : 0;
|
|
|
|
for (int Index = 0; Index < Elems; Index++)
|
|
{
|
|
EmitVectorExtractZx(Context, Op.Rn, Index, Op.Size + 1);
|
|
|
|
EmitVectorInsert(Context, Op.Rd, Part + Index, Op.Size);
|
|
}
|
|
|
|
if (Part == 0)
|
|
{
|
|
EmitVectorZeroUpper(Context, Op.Rd);
|
|
}
|
|
}
|
|
|
|
private static void EmitSimdMemMs(AILEmitterCtx Context, bool IsLoad)
|
|
{
|
|
AOpCodeSimdMemMs Op = (AOpCodeSimdMemMs)Context.CurrOp;
|
|
|
|
int Offset = 0;
|
|
|
|
for (int Rep = 0; Rep < Op.Reps; Rep++)
|
|
for (int Elem = 0; Elem < Op.Elems; Elem++)
|
|
for (int SElem = 0; SElem < Op.SElems; SElem++)
|
|
{
|
|
int Rtt = (Op.Rt + Rep + SElem) & 0x1f;
|
|
|
|
if (IsLoad)
|
|
{
|
|
Context.EmitLdarg(ATranslatedSub.MemoryArgIdx);
|
|
Context.EmitLdint(Op.Rn);
|
|
Context.EmitLdc_I8(Offset);
|
|
|
|
Context.Emit(OpCodes.Add);
|
|
|
|
EmitReadZxCall(Context, Op.Size);
|
|
|
|
EmitVectorInsert(Context, Rtt, Elem, Op.Size);
|
|
|
|
if (Op.RegisterSize == ARegisterSize.SIMD64 && Elem == Op.Elems - 1)
|
|
{
|
|
EmitVectorZeroUpper(Context, Rtt);
|
|
}
|
|
}
|
|
else
|
|
{
|
|
Context.EmitLdarg(ATranslatedSub.MemoryArgIdx);
|
|
Context.EmitLdint(Op.Rn);
|
|
Context.EmitLdc_I8(Offset);
|
|
|
|
Context.Emit(OpCodes.Add);
|
|
|
|
EmitVectorExtractZx(Context, Rtt, Elem, Op.Size);
|
|
|
|
EmitWriteCall(Context, Op.Size);
|
|
}
|
|
|
|
Offset += 1 << Op.Size;
|
|
}
|
|
|
|
if (Op.WBack)
|
|
{
|
|
EmitSimdMemWBack(Context, Offset);
|
|
}
|
|
}
|
|
|
|
private static void EmitSimdMemSs(AILEmitterCtx Context, bool IsLoad)
|
|
{
|
|
AOpCodeSimdMemSs Op = (AOpCodeSimdMemSs)Context.CurrOp;
|
|
|
|
//TODO: Replicate mode.
|
|
|
|
int Offset = 0;
|
|
|
|
for (int SElem = 0; SElem < Op.SElems; SElem++)
|
|
{
|
|
int Rt = (Op.Rt + SElem) & 0x1f;
|
|
|
|
if (IsLoad)
|
|
{
|
|
Context.EmitLdarg(ATranslatedSub.MemoryArgIdx);
|
|
Context.EmitLdint(Op.Rn);
|
|
Context.EmitLdc_I8(Offset);
|
|
|
|
Context.Emit(OpCodes.Add);
|
|
|
|
EmitReadZxCall(Context, Op.Size);
|
|
|
|
EmitVectorInsert(Context, Rt, Op.Index, Op.Size);
|
|
|
|
if (Op.RegisterSize == ARegisterSize.SIMD64)
|
|
{
|
|
EmitVectorZeroUpper(Context, Rt);
|
|
}
|
|
}
|
|
else
|
|
{
|
|
Context.EmitLdarg(ATranslatedSub.MemoryArgIdx);
|
|
Context.EmitLdint(Op.Rn);
|
|
Context.EmitLdc_I8(Offset);
|
|
|
|
Context.Emit(OpCodes.Add);
|
|
|
|
EmitVectorExtractZx(Context, Rt, Op.Index, Op.Size);
|
|
|
|
EmitWriteCall(Context, Op.Size);
|
|
}
|
|
|
|
Offset += 1 << Op.Size;
|
|
}
|
|
|
|
if (Op.WBack)
|
|
{
|
|
EmitSimdMemWBack(Context, Offset);
|
|
}
|
|
}
|
|
|
|
private static void EmitSimdMemWBack(AILEmitterCtx Context, int Offset)
|
|
{
|
|
AOpCodeMemReg Op = (AOpCodeMemReg)Context.CurrOp;
|
|
|
|
Context.EmitLdint(Op.Rn);
|
|
|
|
if (Op.Rm != ARegisters.ZRIndex)
|
|
{
|
|
Context.EmitLdint(Op.Rm);
|
|
}
|
|
else
|
|
{
|
|
Context.EmitLdc_I8(Offset);
|
|
}
|
|
|
|
Context.Emit(OpCodes.Add);
|
|
|
|
Context.EmitStint(Op.Rn);
|
|
}
|
|
|
|
private static void EmitVectorCmp(AILEmitterCtx Context, OpCode ILOp)
|
|
{
|
|
AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
|
|
|
|
int Bytes = Context.CurrOp.GetBitsCount() >> 3;
|
|
|
|
ulong SzMask = ulong.MaxValue >> (64 - (8 << Op.Size));
|
|
|
|
for (int Index = 0; Index < (Bytes >> Op.Size); Index++)
|
|
{
|
|
EmitVectorExtractSx(Context, Op.Rn, Index, Op.Size);
|
|
|
|
if (Op is AOpCodeSimdReg BinOp)
|
|
{
|
|
EmitVectorExtractSx(Context, BinOp.Rm, Index, Op.Size);
|
|
}
|
|
else
|
|
{
|
|
Context.EmitLdc_I8(0);
|
|
}
|
|
|
|
AILLabel LblTrue = new AILLabel();
|
|
AILLabel LblEnd = new AILLabel();
|
|
|
|
Context.Emit(ILOp, LblTrue);
|
|
|
|
EmitVectorInsert(Context, Op.Rd, Index, Op.Size, 0);
|
|
|
|
Context.Emit(OpCodes.Br_S, LblEnd);
|
|
|
|
Context.MarkLabel(LblTrue);
|
|
|
|
EmitVectorInsert(Context, Op.Rd, Index, Op.Size, (long)SzMask);
|
|
|
|
Context.MarkLabel(LblEnd);
|
|
}
|
|
|
|
if (Op.RegisterSize == ARegisterSize.SIMD64)
|
|
{
|
|
EmitVectorZeroUpper(Context, Op.Rd);
|
|
}
|
|
}
|
|
|
|
private static void EmitVectorShl(AILEmitterCtx Context, bool Signed)
|
|
{
|
|
//This instruction shifts the value on vector A by the number of bits
|
|
//specified on the signed, lower 8 bits of vector B. If the shift value
|
|
//is greater or equal to the data size of each lane, then the result is zero.
|
|
//Additionally, negative shifts produces right shifts by the negated shift value.
|
|
AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
|
|
|
|
int MaxShift = 8 << Op.Size;
|
|
|
|
Action Emit = () =>
|
|
{
|
|
AILLabel LblShl = new AILLabel();
|
|
AILLabel LblZero = new AILLabel();
|
|
AILLabel LblEnd = new AILLabel();
|
|
|
|
void EmitShift(OpCode ILOp)
|
|
{
|
|
Context.Emit(OpCodes.Dup);
|
|
|
|
Context.EmitLdc_I4(MaxShift);
|
|
|
|
Context.Emit(OpCodes.Bge_S, LblZero);
|
|
Context.Emit(ILOp);
|
|
Context.Emit(OpCodes.Br_S, LblEnd);
|
|
}
|
|
|
|
Context.Emit(OpCodes.Conv_I1);
|
|
Context.Emit(OpCodes.Dup);
|
|
|
|
Context.EmitLdc_I4(0);
|
|
|
|
Context.Emit(OpCodes.Bge_S, LblShl);
|
|
Context.Emit(OpCodes.Neg);
|
|
|
|
EmitShift(Signed
|
|
? OpCodes.Shr
|
|
: OpCodes.Shr_Un);
|
|
|
|
Context.MarkLabel(LblShl);
|
|
|
|
EmitShift(OpCodes.Shl);
|
|
|
|
Context.MarkLabel(LblZero);
|
|
|
|
Context.Emit(OpCodes.Pop);
|
|
Context.Emit(OpCodes.Pop);
|
|
|
|
Context.EmitLdc_I8(0);
|
|
|
|
Context.MarkLabel(LblEnd);
|
|
};
|
|
|
|
if (Signed)
|
|
{
|
|
EmitVectorBinarySx(Context, Emit);
|
|
}
|
|
else
|
|
{
|
|
EmitVectorBinaryZx(Context, Emit);
|
|
}
|
|
}
|
|
|
|
private static void EmitVectorFcvt(AILEmitterCtx Context, bool Signed)
|
|
{
|
|
AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
|
|
|
|
int SizeF = Op.Size & 1;
|
|
int SizeI = SizeF + 2;
|
|
|
|
int FBits = GetFBits(Context);
|
|
|
|
int Bytes = Context.CurrOp.GetBitsCount() >> 3;
|
|
|
|
for (int Index = 0; Index < (Bytes >> SizeI); Index++)
|
|
{
|
|
EmitVectorExtractF(Context, Op.Rn, Index, SizeF);
|
|
|
|
Context.EmitLdc_I4(FBits);
|
|
|
|
if (SizeF == 0)
|
|
{
|
|
ASoftFallback.EmitCall(Context, Signed
|
|
? nameof(ASoftFallback.SatSingleToInt32)
|
|
: nameof(ASoftFallback.SatSingleToUInt32));
|
|
}
|
|
else if (SizeF == 1)
|
|
{
|
|
ASoftFallback.EmitCall(Context, Signed
|
|
? nameof(ASoftFallback.SatDoubleToInt64)
|
|
: nameof(ASoftFallback.SatDoubleToUInt64));
|
|
}
|
|
|
|
EmitVectorInsert(Context, Op.Rd, Index, SizeI);
|
|
}
|
|
|
|
if (Op.RegisterSize == ARegisterSize.SIMD64)
|
|
{
|
|
EmitVectorZeroUpper(Context, Op.Rd);
|
|
}
|
|
}
|
|
|
|
private static void EmitVectorCvtf(AILEmitterCtx Context, bool Signed)
|
|
{
|
|
AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
|
|
|
|
int SizeF = Op.Size & 1;
|
|
int SizeI = SizeF + 2;
|
|
|
|
int FBits = GetFBits(Context);
|
|
|
|
int Bytes = Context.CurrOp.GetBitsCount() >> 3;
|
|
|
|
for (int Index = 0; Index < (Bytes >> SizeI); Index++)
|
|
{
|
|
EmitVectorExtract(Context, Op.Rn, Index, SizeI, Signed);
|
|
|
|
Context.EmitLdc_I4(FBits);
|
|
|
|
if (SizeF == 0)
|
|
{
|
|
Context.Emit(OpCodes.Conv_I4);
|
|
|
|
ASoftFallback.EmitCall(Context, Signed
|
|
? nameof(ASoftFallback.Int32ToSingle)
|
|
: nameof(ASoftFallback.UInt32ToSingle));
|
|
}
|
|
else if (SizeF == 1)
|
|
{
|
|
ASoftFallback.EmitCall(Context, Signed
|
|
? nameof(ASoftFallback.Int64ToDouble)
|
|
: nameof(ASoftFallback.UInt64ToDouble));
|
|
}
|
|
|
|
EmitVectorInsertF(Context, Op.Rd, Index, SizeF);
|
|
}
|
|
|
|
if (Op.RegisterSize == ARegisterSize.SIMD64)
|
|
{
|
|
EmitVectorZeroUpper(Context, Op.Rd);
|
|
}
|
|
}
|
|
|
|
private static int GetFBits(AILEmitterCtx Context)
|
|
{
|
|
if (Context.CurrOp is AOpCodeSimdShImm Op)
|
|
{
|
|
return (8 << (Op.Size + 1)) - Op.Imm;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
[Flags]
|
|
private enum OperFlags
|
|
{
|
|
Rd = 1 << 0,
|
|
Rn = 1 << 1,
|
|
Rm = 1 << 2,
|
|
|
|
RnRm = Rn | Rm,
|
|
RdRn = Rd | Rn,
|
|
RdRnRm = Rd | Rn | Rm
|
|
}
|
|
|
|
private static void EmitVectorBinaryF(AILEmitterCtx Context, Action Emit)
|
|
{
|
|
EmitVectorFOp(Context, Emit, OperFlags.RnRm);
|
|
}
|
|
|
|
private static void EmitVectorTernaryF(AILEmitterCtx Context, Action Emit)
|
|
{
|
|
EmitVectorFOp(Context, Emit, OperFlags.RdRnRm);
|
|
}
|
|
|
|
private static void EmitVectorBinaryByElemF(AILEmitterCtx Context, Action Emit)
|
|
{
|
|
AOpCodeSimdRegElem Op = (AOpCodeSimdRegElem)Context.CurrOp;
|
|
|
|
EmitVectorFOp(Context, Emit, OperFlags.RnRm, Op.Index);
|
|
}
|
|
|
|
private static void EmitVectorTernaryByElemF(AILEmitterCtx Context, Action Emit)
|
|
{
|
|
AOpCodeSimdRegElem Op = (AOpCodeSimdRegElem)Context.CurrOp;
|
|
|
|
EmitVectorFOp(Context, Emit, OperFlags.RdRnRm, Op.Index);
|
|
}
|
|
|
|
private static void EmitVectorFOp(AILEmitterCtx Context, Action Emit, OperFlags Opers, int Elem = -1)
|
|
{
|
|
AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp;
|
|
|
|
int SizeF = Op.Size & 1;
|
|
|
|
int Bytes = Context.CurrOp.GetBitsCount() >> 3;
|
|
|
|
for (int Index = 0; Index < (Bytes >> SizeF + 2); Index++)
|
|
{
|
|
if (Opers.HasFlag(OperFlags.Rd))
|
|
{
|
|
EmitVectorExtractF(Context, Op.Rd, Index, SizeF);
|
|
}
|
|
|
|
if (Opers.HasFlag(OperFlags.Rn))
|
|
{
|
|
EmitVectorExtractF(Context, Op.Rn, Index, SizeF);
|
|
}
|
|
|
|
if (Opers.HasFlag(OperFlags.Rm))
|
|
{
|
|
if (Elem != -1)
|
|
{
|
|
EmitVectorExtractF(Context, Op.Rm, Elem, SizeF);
|
|
}
|
|
else
|
|
{
|
|
EmitVectorExtractF(Context, Op.Rm, Index, SizeF);
|
|
}
|
|
}
|
|
|
|
Emit();
|
|
|
|
EmitVectorInsertF(Context, Op.Rd, Index, SizeF);
|
|
}
|
|
|
|
if (Op.RegisterSize == ARegisterSize.SIMD64)
|
|
{
|
|
EmitVectorZeroUpper(Context, Op.Rd);
|
|
}
|
|
}
|
|
|
|
private static void EmitVectorUnarySx(AILEmitterCtx Context, Action Emit)
|
|
{
|
|
EmitVectorOp(Context, Emit, OperFlags.Rn, true);
|
|
}
|
|
|
|
private static void EmitVectorBinarySx(AILEmitterCtx Context, Action Emit)
|
|
{
|
|
EmitVectorOp(Context, Emit, OperFlags.RnRm, true);
|
|
}
|
|
|
|
private static void EmitVectorUnaryZx(AILEmitterCtx Context, Action Emit)
|
|
{
|
|
EmitVectorOp(Context, Emit, OperFlags.Rn, false);
|
|
}
|
|
|
|
private static void EmitVectorBinaryZx(AILEmitterCtx Context, Action Emit)
|
|
{
|
|
EmitVectorOp(Context, Emit, OperFlags.RnRm, false);
|
|
}
|
|
|
|
private static void EmitVectorTernaryZx(AILEmitterCtx Context, Action Emit)
|
|
{
|
|
EmitVectorOp(Context, Emit, OperFlags.RdRnRm, false);
|
|
}
|
|
|
|
private static void EmitVectorOp(AILEmitterCtx Context, Action Emit, OperFlags Opers, bool Signed)
|
|
{
|
|
AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
|
|
|
|
int Bytes = Context.CurrOp.GetBitsCount() >> 3;
|
|
|
|
for (int Index = 0; Index < (Bytes >> Op.Size); Index++)
|
|
{
|
|
if (Opers.HasFlag(OperFlags.Rd))
|
|
{
|
|
EmitVectorExtract(Context, Op.Rd, Index, Op.Size, Signed);
|
|
}
|
|
|
|
if (Opers.HasFlag(OperFlags.Rn))
|
|
{
|
|
EmitVectorExtract(Context, Op.Rn, Index, Op.Size, Signed);
|
|
}
|
|
|
|
if (Opers.HasFlag(OperFlags.Rm))
|
|
{
|
|
EmitVectorExtract(Context, ((AOpCodeSimdReg)Op).Rm, Index, Op.Size, Signed);
|
|
}
|
|
|
|
Emit();
|
|
|
|
EmitVectorInsert(Context, Op.Rd, Index, Op.Size);
|
|
}
|
|
|
|
if (Op.RegisterSize == ARegisterSize.SIMD64)
|
|
{
|
|
EmitVectorZeroUpper(Context, Op.Rd);
|
|
}
|
|
}
|
|
|
|
private static void EmitVectorImmUnary(AILEmitterCtx Context, Action Emit)
|
|
{
|
|
EmitVectorImmOp(Context, Emit, false);
|
|
}
|
|
|
|
private static void EmitVectorImmBinary(AILEmitterCtx Context, Action Emit)
|
|
{
|
|
EmitVectorImmOp(Context, Emit, true);
|
|
}
|
|
|
|
private static void EmitVectorImmOp(AILEmitterCtx Context, Action Emit, bool Binary)
|
|
{
|
|
AOpCodeSimdImm Op = (AOpCodeSimdImm)Context.CurrOp;
|
|
|
|
int Bytes = Context.CurrOp.GetBitsCount() >> 3;
|
|
|
|
for (int Index = 0; Index < (Bytes >> Op.Size); Index++)
|
|
{
|
|
if (Binary)
|
|
{
|
|
EmitVectorExtractZx(Context, Op.Rd, Index, Op.Size);
|
|
}
|
|
|
|
Context.EmitLdc_I8(Op.Imm);
|
|
|
|
Emit();
|
|
|
|
EmitVectorInsert(Context, Op.Rd, Index, Op.Size);
|
|
}
|
|
|
|
if (Op.RegisterSize == ARegisterSize.SIMD64)
|
|
{
|
|
EmitVectorZeroUpper(Context, Op.Rd);
|
|
}
|
|
}
|
|
|
|
private static void EmitVectorShImmBinarySx(AILEmitterCtx Context, Action Emit, int Imm)
|
|
{
|
|
EmitVectorShImmBinaryOp(Context, Emit, Imm, true);
|
|
}
|
|
|
|
private static void EmitVectorShImmBinaryZx(AILEmitterCtx Context, Action Emit, int Imm)
|
|
{
|
|
EmitVectorShImmBinaryOp(Context, Emit, Imm, false);
|
|
}
|
|
|
|
private static void EmitVectorShImmBinaryOp(AILEmitterCtx Context, Action Emit, int Imm, bool Signed)
|
|
{
|
|
AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp;
|
|
|
|
int Bytes = Context.CurrOp.GetBitsCount() >> 3;
|
|
|
|
for (int Index = 0; Index < (Bytes >> Op.Size); Index++)
|
|
{
|
|
EmitVectorExtract(Context, Op.Rn, Index, Op.Size, Signed);
|
|
|
|
Context.EmitLdc_I4(Imm);
|
|
|
|
Emit();
|
|
|
|
EmitVectorInsert(Context, Op.Rd, Index, Op.Size);
|
|
}
|
|
|
|
if (Op.RegisterSize == ARegisterSize.SIMD64)
|
|
{
|
|
EmitVectorZeroUpper(Context, Op.Rd);
|
|
}
|
|
}
|
|
|
|
private static void EmitVectorShImmNarrowBinarySx(AILEmitterCtx Context, Action Emit, int Imm)
|
|
{
|
|
EmitVectorShImmNarrowBinaryOp(Context, Emit, Imm, true);
|
|
}
|
|
|
|
private static void EmitVectorShImmNarrowBinaryZx(AILEmitterCtx Context, Action Emit, int Imm)
|
|
{
|
|
EmitVectorShImmNarrowBinaryOp(Context, Emit, Imm, false);
|
|
}
|
|
|
|
private static void EmitVectorShImmNarrowBinaryOp(AILEmitterCtx Context, Action Emit, int Imm, bool Signed)
|
|
{
|
|
AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp;
|
|
|
|
int Elems = 8 >> Op.Size;
|
|
|
|
int Part = Op.RegisterSize == ARegisterSize.SIMD128 ? Elems : 0;
|
|
|
|
for (int Index = 0; Index < Elems; Index++)
|
|
{
|
|
EmitVectorExtract(Context, Op.Rn, Index, Op.Size + 1, Signed);
|
|
|
|
Context.EmitLdc_I4(Imm);
|
|
|
|
Emit();
|
|
|
|
EmitVectorInsert(Context, Op.Rd, Part + Index, Op.Size);
|
|
}
|
|
|
|
if (Part == 0)
|
|
{
|
|
EmitVectorZeroUpper(Context, Op.Rd);
|
|
}
|
|
}
|
|
|
|
private static void EmitVectorShImmWidenBinarySx(AILEmitterCtx Context, Action Emit, int Imm)
|
|
{
|
|
EmitVectorShImmWidenBinaryOp(Context, Emit, Imm, true);
|
|
}
|
|
|
|
private static void EmitVectorShImmWidenBinaryZx(AILEmitterCtx Context, Action Emit, int Imm)
|
|
{
|
|
EmitVectorShImmWidenBinaryOp(Context, Emit, Imm, false);
|
|
}
|
|
|
|
private static void EmitVectorShImmWidenBinaryOp(AILEmitterCtx Context, Action Emit, int Imm, bool Signed)
|
|
{
|
|
AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp;
|
|
|
|
int Elems = 8 >> Op.Size;
|
|
|
|
int Part = Op.RegisterSize == ARegisterSize.SIMD128 ? Elems : 0;
|
|
|
|
for (int Index = 0; Index < Elems; Index++)
|
|
{
|
|
EmitVectorExtract(Context, Op.Rn, Part + Index, Op.Size, Signed);
|
|
|
|
Context.EmitLdc_I4(Imm);
|
|
|
|
Emit();
|
|
|
|
EmitVectorInsertTmp(Context, Index, Op.Size + 1);
|
|
}
|
|
|
|
Context.EmitLdvectmp();
|
|
Context.EmitStvec(Op.Rd);
|
|
}
|
|
|
|
private static void EmitVectorWidenBinarySx(AILEmitterCtx Context, Action Emit)
|
|
{
|
|
EmitVectorWidenBinary(Context, Emit, true);
|
|
}
|
|
|
|
private static void EmitVectorWidenBinaryZx(AILEmitterCtx Context, Action Emit)
|
|
{
|
|
EmitVectorWidenBinary(Context, Emit, false);
|
|
}
|
|
|
|
private static void EmitVectorWidenBinary(AILEmitterCtx Context, Action Emit, bool Signed)
|
|
{
|
|
AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp;
|
|
|
|
int Elems = 8 >> Op.Size;
|
|
|
|
int Part = Op.RegisterSize == ARegisterSize.SIMD128 ? Elems : 0;
|
|
|
|
for (int Index = 0; Index < Elems; Index++)
|
|
{
|
|
EmitVectorExtract(Context, Op.Rn, Index, Op.Size + 1, Signed);
|
|
EmitVectorExtract(Context, Op.Rm, Part + Index, Op.Size, Signed);
|
|
|
|
Emit();
|
|
|
|
EmitVectorInsertTmp(Context, Index, Op.Size + 1);
|
|
}
|
|
|
|
Context.EmitLdvectmp();
|
|
Context.EmitStvec(Op.Rd);
|
|
}
|
|
|
|
private static void EmitVectorExtractF(AILEmitterCtx Context, int Reg, int Index, int Size)
|
|
{
|
|
Context.EmitLdvec(Reg);
|
|
Context.EmitLdc_I4(Index);
|
|
|
|
if (Size == 0)
|
|
{
|
|
ASoftFallback.EmitCall(Context, nameof(ASoftFallback.VectorExtractSingle));
|
|
}
|
|
else if (Size == 1)
|
|
{
|
|
ASoftFallback.EmitCall(Context, nameof(ASoftFallback.VectorExtractDouble));
|
|
}
|
|
else
|
|
{
|
|
throw new ArgumentOutOfRangeException(nameof(Size));
|
|
}
|
|
}
|
|
|
|
private static void EmitVectorExtractSx(AILEmitterCtx Context, int Reg, int Index, int Size)
|
|
{
|
|
EmitVectorExtract(Context, Reg, Index, Size, true);
|
|
}
|
|
|
|
private static void EmitVectorExtractZx(AILEmitterCtx Context, int Reg, int Index, int Size)
|
|
{
|
|
EmitVectorExtract(Context, Reg, Index, Size, false);
|
|
}
|
|
|
|
private static void EmitVectorExtract(AILEmitterCtx Context, int Reg, int Index, int Size, bool Signed)
|
|
{
|
|
if (Size < 0 || Size > 3)
|
|
{
|
|
throw new ArgumentOutOfRangeException(nameof(Size));
|
|
}
|
|
|
|
IAOpCodeSimd Op = (IAOpCodeSimd)Context.CurrOp;
|
|
|
|
Context.EmitLdvec(Reg);
|
|
Context.EmitLdc_I4(Index);
|
|
Context.EmitLdc_I4(Size);
|
|
|
|
ASoftFallback.EmitCall(Context, Signed
|
|
? nameof(ASoftFallback.ExtractSVec)
|
|
: nameof(ASoftFallback.ExtractVec));
|
|
}
|
|
|
|
private static void EmitVectorZeroLower(AILEmitterCtx Context, int Rd)
|
|
{
|
|
EmitVectorInsert(Context, Rd, 0, 3, 0);
|
|
}
|
|
|
|
private static void EmitVectorZeroUpper(AILEmitterCtx Context, int Rd)
|
|
{
|
|
EmitVectorInsert(Context, Rd, 1, 3, 0);
|
|
}
|
|
|
|
private static void EmitVectorInsertF(AILEmitterCtx Context, int Reg, int Index, int Size)
|
|
{
|
|
Context.EmitLdvec(Reg);
|
|
Context.EmitLdc_I4(Index);
|
|
|
|
if (Size == 0)
|
|
{
|
|
ASoftFallback.EmitCall(Context, nameof(ASoftFallback.VectorInsertSingle));
|
|
}
|
|
else if (Size == 1)
|
|
{
|
|
ASoftFallback.EmitCall(Context, nameof(ASoftFallback.VectorInsertDouble));
|
|
}
|
|
else
|
|
{
|
|
throw new ArgumentOutOfRangeException(nameof(Size));
|
|
}
|
|
|
|
Context.EmitStvec(Reg);
|
|
}
|
|
|
|
private static void EmitVectorInsertTmp(AILEmitterCtx Context, int Index, int Size)
|
|
{
|
|
if (Size < 0 || Size > 3)
|
|
{
|
|
throw new ArgumentOutOfRangeException(nameof(Size));
|
|
}
|
|
|
|
Context.EmitLdvectmp();
|
|
Context.EmitLdc_I4(Index);
|
|
Context.EmitLdc_I4(Size);
|
|
|
|
ASoftFallback.EmitCall(Context, nameof(ASoftFallback.VectorInsertInt));
|
|
|
|
Context.EmitStvectmp();
|
|
}
|
|
|
|
private static void EmitVectorInsert(AILEmitterCtx Context, int Reg, int Index, int Size)
|
|
{
|
|
if (Size < 0 || Size > 3)
|
|
{
|
|
throw new ArgumentOutOfRangeException(nameof(Size));
|
|
}
|
|
|
|
Context.EmitLdvec(Reg);
|
|
Context.EmitLdc_I4(Index);
|
|
Context.EmitLdc_I4(Size);
|
|
|
|
ASoftFallback.EmitCall(Context, nameof(ASoftFallback.VectorInsertInt));
|
|
|
|
Context.EmitStvec(Reg);
|
|
}
|
|
|
|
private static void EmitVectorInsert(AILEmitterCtx Context, int Reg, int Index, int Size, long Value)
|
|
{
|
|
if (Size < 0 || Size > 3)
|
|
{
|
|
throw new ArgumentOutOfRangeException(nameof(Size));
|
|
}
|
|
|
|
Context.EmitLdvec(Reg);
|
|
Context.EmitLdc_I4(Index);
|
|
Context.EmitLdc_I4(Size);
|
|
Context.EmitLdc_I8(Value);
|
|
|
|
ASoftFallback.EmitCall(Context, nameof(ASoftFallback.InsertVec));
|
|
|
|
Context.EmitStvec(Reg);
|
|
}
|
|
}
|
|
} |