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2f16491712
* Get rid of Reflection.Emit dependency on CPU and Shader projects * Remove useless private sets * Missed those due to the alignment
97 lines
No EOL
2.4 KiB
C#
97 lines
No EOL
2.4 KiB
C#
namespace ARMeilleure.Decoders
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{
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class OpCodeSimdMemSs : OpCodeMemReg, IOpCodeSimd
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{
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public int SElems { get; }
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public int Index { get; }
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public bool Replicate { get; }
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public bool WBack { get; }
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public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdMemSs(inst, address, opCode);
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public OpCodeSimdMemSs(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
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{
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int size = (opCode >> 10) & 3;
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int s = (opCode >> 12) & 1;
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int sElems = (opCode >> 12) & 2;
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int scale = (opCode >> 14) & 3;
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int l = (opCode >> 22) & 1;
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int q = (opCode >> 30) & 1;
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sElems |= (opCode >> 21) & 1;
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sElems++;
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int index = (q << 3) | (s << 2) | size;
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switch (scale)
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{
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case 1:
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{
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if ((size & 1) != 0)
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{
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Instruction = InstDescriptor.Undefined;
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return;
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}
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index >>= 1;
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break;
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}
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case 2:
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{
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if ((size & 2) != 0 ||
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((size & 1) != 0 && s != 0))
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{
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Instruction = InstDescriptor.Undefined;
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return;
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}
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if ((size & 1) != 0)
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{
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index >>= 3;
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scale = 3;
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}
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else
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{
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index >>= 2;
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}
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break;
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}
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case 3:
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{
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if (l == 0 || s != 0)
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{
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Instruction = InstDescriptor.Undefined;
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return;
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}
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scale = size;
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Replicate = true;
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break;
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}
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}
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Index = index;
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SElems = sElems;
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Size = scale;
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Extend64 = false;
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WBack = ((opCode >> 23) & 1) != 0;
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RegisterSize = q != 0
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? RegisterSize.Simd128
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: RegisterSize.Simd64;
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}
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}
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} |