mirror of
https://github.com/ryujinx-mirror/ryujinx.git
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ce1d5be212
* Move GPU LLE emulation from HLE to Graphics * Graphics: Move Gal/Texture to Texture * Remove Engines/ directory and namespace * Use tables for image formats * Abstract OpCode decoding * Simplify image table * Do not leak Read* symbols in TextureReader * Fixups * Rename IGalFrameBuffer -> IGalRenderTarget * Remove MaxBpp hardcoded value * Change yet again texture data and add G8R8 flipping * Rename GalFrameBufferFormat to GalSurfaceFormat * Unident EnsureSetup in ImageHandler * Add IsCompressed * Address some feedback
143 lines
No EOL
4.4 KiB
C#
143 lines
No EOL
4.4 KiB
C#
using Ryujinx.Graphics.Memory;
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using Ryujinx.Graphics.Texture;
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using System.Collections.Generic;
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namespace Ryujinx.Graphics
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{
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public class NvGpuEngineDma : INvGpuEngine
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{
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public int[] Registers { get; private set; }
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private NvGpu Gpu;
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private Dictionary<int, NvGpuMethod> Methods;
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public NvGpuEngineDma(NvGpu Gpu)
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{
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this.Gpu = Gpu;
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Registers = new int[0x1d6];
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Methods = new Dictionary<int, NvGpuMethod>();
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void AddMethod(int Meth, int Count, int Stride, NvGpuMethod Method)
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{
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while (Count-- > 0)
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{
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Methods.Add(Meth, Method);
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Meth += Stride;
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}
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}
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AddMethod(0xc0, 1, 1, Execute);
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}
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public void CallMethod(NvGpuVmm Vmm, NvGpuPBEntry PBEntry)
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{
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if (Methods.TryGetValue(PBEntry.Method, out NvGpuMethod Method))
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{
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Method(Vmm, PBEntry);
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}
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else
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{
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WriteRegister(PBEntry);
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}
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}
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private void Execute(NvGpuVmm Vmm, NvGpuPBEntry PBEntry)
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{
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int Control = PBEntry.Arguments[0];
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bool SrcLinear = ((Control >> 7) & 1) != 0;
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bool DstLinear = ((Control >> 8) & 1) != 0;
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long SrcAddress = MakeInt64From2xInt32(NvGpuEngineDmaReg.SrcAddress);
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long DstAddress = MakeInt64From2xInt32(NvGpuEngineDmaReg.DstAddress);
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int SrcPitch = ReadRegister(NvGpuEngineDmaReg.SrcPitch);
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int DstPitch = ReadRegister(NvGpuEngineDmaReg.DstPitch);
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int DstBlkDim = ReadRegister(NvGpuEngineDmaReg.DstBlkDim);
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int DstSizeX = ReadRegister(NvGpuEngineDmaReg.DstSizeX);
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int DstSizeY = ReadRegister(NvGpuEngineDmaReg.DstSizeY);
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int DstSizeZ = ReadRegister(NvGpuEngineDmaReg.DstSizeZ);
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int DstPosXY = ReadRegister(NvGpuEngineDmaReg.DstPosXY);
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int DstPosZ = ReadRegister(NvGpuEngineDmaReg.DstPosZ);
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int SrcBlkDim = ReadRegister(NvGpuEngineDmaReg.SrcBlkDim);
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int SrcSizeX = ReadRegister(NvGpuEngineDmaReg.SrcSizeX);
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int SrcSizeY = ReadRegister(NvGpuEngineDmaReg.SrcSizeY);
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int SrcSizeZ = ReadRegister(NvGpuEngineDmaReg.SrcSizeZ);
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int SrcPosXY = ReadRegister(NvGpuEngineDmaReg.SrcPosXY);
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int SrcPosZ = ReadRegister(NvGpuEngineDmaReg.SrcPosZ);
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int DstPosX = (DstPosXY >> 0) & 0xffff;
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int DstPosY = (DstPosXY >> 16) & 0xffff;
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int SrcPosX = (SrcPosXY >> 0) & 0xffff;
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int SrcPosY = (SrcPosXY >> 16) & 0xffff;
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int SrcBlockHeight = 1 << ((SrcBlkDim >> 4) & 0xf);
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int DstBlockHeight = 1 << ((DstBlkDim >> 4) & 0xf);
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ISwizzle SrcSwizzle;
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if (SrcLinear)
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{
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SrcSwizzle = new LinearSwizzle(SrcPitch, 1);
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}
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else
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{
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SrcSwizzle = new BlockLinearSwizzle(SrcSizeX, 1, SrcBlockHeight);
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}
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ISwizzle DstSwizzle;
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if (DstLinear)
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{
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DstSwizzle = new LinearSwizzle(DstPitch, 1);
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}
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else
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{
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DstSwizzle = new BlockLinearSwizzle(DstSizeX, 1, DstBlockHeight);
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}
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for (int Y = 0; Y < DstSizeY; Y++)
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for (int X = 0; X < DstSizeX; X++)
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{
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long SrcOffset = SrcAddress + (uint)SrcSwizzle.GetSwizzleOffset(X, Y);
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long DstOffset = DstAddress + (uint)DstSwizzle.GetSwizzleOffset(X, Y);
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Vmm.WriteByte(DstOffset, Vmm.ReadByte(SrcOffset));
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}
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}
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private long MakeInt64From2xInt32(NvGpuEngineDmaReg Reg)
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{
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return
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(long)Registers[(int)Reg + 0] << 32 |
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(uint)Registers[(int)Reg + 1];
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}
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private void WriteRegister(NvGpuPBEntry PBEntry)
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{
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int ArgsCount = PBEntry.Arguments.Count;
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if (ArgsCount > 0)
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{
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Registers[PBEntry.Method] = PBEntry.Arguments[ArgsCount - 1];
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}
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}
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private int ReadRegister(NvGpuEngineDmaReg Reg)
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{
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return Registers[(int)Reg];
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}
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private void WriteRegister(NvGpuEngineDmaReg Reg, int Value)
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{
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Registers[(int)Reg] = Value;
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}
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}
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} |