mirror of
https://github.com/ryujinx-mirror/ryujinx.git
synced 2024-12-24 03:05:45 +00:00
517 lines
20 KiB
C#
517 lines
20 KiB
C#
using Ryujinx.Graphics.Gpu.State;
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using System;
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using System.Collections.Generic;
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using System.Reflection.Emit;
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namespace Ryujinx.Graphics.Gpu.Engine.MME
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{
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/// <summary>
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/// Represents a Macro Just-in-Time compiler.
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/// </summary>R
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class MacroJitCompiler
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{
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private readonly DynamicMethod _meth;
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private readonly ILGenerator _ilGen;
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private readonly LocalBuilder[] _gprs;
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private readonly LocalBuilder _carry;
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private readonly LocalBuilder _methAddr;
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private readonly LocalBuilder _methIncr;
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/// <summary>
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/// Creates a new instance of the Macro Just-in-Time compiler.
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/// </summary>
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public MacroJitCompiler()
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{
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_meth = new DynamicMethod("Macro", typeof(void), new Type[] { typeof(MacroJitContext), typeof(GpuState), typeof(int) });
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_ilGen = _meth.GetILGenerator();
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_gprs = new LocalBuilder[8];
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for (int i = 1; i < 8; i++)
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{
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_gprs[i] = _ilGen.DeclareLocal(typeof(int));
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}
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_carry = _ilGen.DeclareLocal(typeof(int));
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_methAddr = _ilGen.DeclareLocal(typeof(int));
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_methIncr = _ilGen.DeclareLocal(typeof(int));
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_ilGen.Emit(OpCodes.Ldarg_2);
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_ilGen.Emit(OpCodes.Stloc, _gprs[1]);
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}
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public delegate void MacroExecute(MacroJitContext context, GpuState state, int arg0);
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/// <summary>
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/// Translates a new piece of GPU Macro code into host executable code.
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/// </summary>
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/// <param name="code">Code to be translated</param>
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/// <returns>Delegate of the host compiled code</returns>
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public MacroExecute Compile(ReadOnlySpan<int> code)
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{
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Dictionary<int, Label> labels = new Dictionary<int, Label>();
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int lastTarget = 0;
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int i;
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// Collect all branch targets.
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for (i = 0; i < code.Length; i++)
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{
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int opCode = code[i];
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if ((opCode & 7) == 7)
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{
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int target = i + (opCode >> 14);
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if (!labels.ContainsKey(target))
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{
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labels.Add(target, _ilGen.DefineLabel());
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}
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if (lastTarget < target)
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{
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lastTarget = target;
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}
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}
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bool exit = (opCode & 0x80) != 0;
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if (exit && i >= lastTarget)
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{
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break;
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}
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}
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// Code generation.
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for (i = 0; i < code.Length; i++)
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{
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if (labels.TryGetValue(i, out Label label))
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{
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_ilGen.MarkLabel(label);
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}
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Emit(code, i, labels);
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int opCode = code[i];
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bool exit = (opCode & 0x80) != 0;
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if (exit)
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{
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Emit(code, i + 1, labels);
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_ilGen.Emit(OpCodes.Ret);
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if (i >= lastTarget)
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{
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break;
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}
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}
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}
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if (i == code.Length)
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{
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_ilGen.Emit(OpCodes.Ret);
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}
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return (MacroExecute)_meth.CreateDelegate(typeof(MacroExecute));
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}
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/// <summary>
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/// Emits IL equivalent to the Macro instruction at a given offset.
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/// </summary>
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/// <param name="code">GPU Macro code</param>
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/// <param name="offset">Offset, in words, where the instruction is located</param>
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/// <param name="labels">Labels for Macro branch targets, used by branch instructions</param>
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private void Emit(ReadOnlySpan<int> code, int offset, Dictionary<int, Label> labels)
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{
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int opCode = code[offset];
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if ((opCode & 7) < 7)
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{
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// Operation produces a value.
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AssignmentOperation asgOp = (AssignmentOperation)((opCode >> 4) & 7);
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EmitAluOp(opCode);
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switch (asgOp)
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{
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// Fetch parameter and ignore result.
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case AssignmentOperation.IgnoreAndFetch:
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_ilGen.Emit(OpCodes.Pop);
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EmitFetchParam();
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EmitStoreDstGpr(opCode);
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break;
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// Move result.
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case AssignmentOperation.Move:
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EmitStoreDstGpr(opCode);
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break;
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// Move result and use as Method Address.
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case AssignmentOperation.MoveAndSetMaddr:
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_ilGen.Emit(OpCodes.Dup);
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EmitStoreDstGpr(opCode);
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EmitStoreMethAddr();
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break;
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// Fetch parameter and send result.
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case AssignmentOperation.FetchAndSend:
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EmitFetchParam();
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EmitStoreDstGpr(opCode);
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EmitSend();
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break;
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// Move and send result.
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case AssignmentOperation.MoveAndSend:
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_ilGen.Emit(OpCodes.Dup);
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EmitStoreDstGpr(opCode);
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EmitSend();
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break;
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// Fetch parameter and use result as Method Address.
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case AssignmentOperation.FetchAndSetMaddr:
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EmitFetchParam();
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EmitStoreDstGpr(opCode);
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EmitStoreMethAddr();
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break;
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// Move result and use as Method Address, then fetch and send parameter.
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case AssignmentOperation.MoveAndSetMaddrThenFetchAndSend:
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_ilGen.Emit(OpCodes.Dup);
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EmitStoreDstGpr(opCode);
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EmitStoreMethAddr();
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EmitFetchParam();
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EmitSend();
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break;
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// Move result and use as Method Address, then send bits 17:12 of result.
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case AssignmentOperation.MoveAndSetMaddrThenSendHigh:
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_ilGen.Emit(OpCodes.Dup);
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_ilGen.Emit(OpCodes.Dup);
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EmitStoreDstGpr(opCode);
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EmitStoreMethAddr();
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_ilGen.Emit(OpCodes.Ldc_I4, 12);
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_ilGen.Emit(OpCodes.Shr_Un);
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_ilGen.Emit(OpCodes.Ldc_I4, 0x3f);
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_ilGen.Emit(OpCodes.And);
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EmitSend();
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break;
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}
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}
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else
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{
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// Branch.
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bool onNotZero = ((opCode >> 4) & 1) != 0;
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EmitLoadGprA(opCode);
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Label lblSkip = _ilGen.DefineLabel();
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if (onNotZero)
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{
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_ilGen.Emit(OpCodes.Brfalse, lblSkip);
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}
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else
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{
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_ilGen.Emit(OpCodes.Brtrue, lblSkip);
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}
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bool noDelays = (opCode & 0x20) != 0;
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if (!noDelays)
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{
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Emit(code, offset + 1, labels);
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}
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int target = offset + (opCode >> 14);
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_ilGen.Emit(OpCodes.Br, labels[target]);
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_ilGen.MarkLabel(lblSkip);
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}
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}
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/// <summary>
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/// Emits IL for a Arithmetic and Logic Unit instruction.
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/// </summary>
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/// <param name="opCode">Instruction to be translated</param>
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/// <exception cref="InvalidOperationException">Throw when the instruction encoding is invalid</exception>
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private void EmitAluOp(int opCode)
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{
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AluOperation op = (AluOperation)(opCode & 7);
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switch (op)
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{
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case AluOperation.AluReg:
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EmitAluOp((AluRegOperation)((opCode >> 17) & 0x1f), opCode);
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break;
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case AluOperation.AddImmediate:
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EmitLoadGprA(opCode);
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EmitLoadImm(opCode);
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_ilGen.Emit(OpCodes.Add);
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break;
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case AluOperation.BitfieldReplace:
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case AluOperation.BitfieldExtractLslImm:
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case AluOperation.BitfieldExtractLslReg:
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int bfSrcBit = (opCode >> 17) & 0x1f;
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int bfSize = (opCode >> 22) & 0x1f;
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int bfDstBit = (opCode >> 27) & 0x1f;
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int bfMask = (1 << bfSize) - 1;
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switch (op)
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{
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case AluOperation.BitfieldReplace:
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EmitLoadGprB(opCode);
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_ilGen.Emit(OpCodes.Ldc_I4, bfSrcBit);
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_ilGen.Emit(OpCodes.Shr_Un);
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_ilGen.Emit(OpCodes.Ldc_I4, bfMask);
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_ilGen.Emit(OpCodes.And);
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_ilGen.Emit(OpCodes.Ldc_I4, bfDstBit);
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_ilGen.Emit(OpCodes.Shl);
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EmitLoadGprA(opCode);
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_ilGen.Emit(OpCodes.Ldc_I4, ~(bfMask << bfDstBit));
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_ilGen.Emit(OpCodes.And);
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_ilGen.Emit(OpCodes.Or);
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break;
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case AluOperation.BitfieldExtractLslImm:
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EmitLoadGprB(opCode);
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EmitLoadGprA(opCode);
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_ilGen.Emit(OpCodes.Shr_Un);
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_ilGen.Emit(OpCodes.Ldc_I4, bfMask);
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_ilGen.Emit(OpCodes.And);
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_ilGen.Emit(OpCodes.Ldc_I4, bfDstBit);
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_ilGen.Emit(OpCodes.Shl);
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break;
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case AluOperation.BitfieldExtractLslReg:
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EmitLoadGprB(opCode);
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_ilGen.Emit(OpCodes.Ldc_I4, bfSrcBit);
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_ilGen.Emit(OpCodes.Shr_Un);
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_ilGen.Emit(OpCodes.Ldc_I4, bfMask);
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_ilGen.Emit(OpCodes.And);
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EmitLoadGprA(opCode);
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_ilGen.Emit(OpCodes.Shl);
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break;
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}
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break;
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case AluOperation.ReadImmediate:
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_ilGen.Emit(OpCodes.Ldarg_1);
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EmitLoadGprA(opCode);
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EmitLoadImm(opCode);
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_ilGen.Emit(OpCodes.Add);
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_ilGen.Emit(OpCodes.Call, typeof(MacroJitContext).GetMethod(nameof(MacroJitContext.Read)));
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break;
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default:
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throw new InvalidOperationException($"Invalid operation \"{op}\" on instruction 0x{opCode:X8}.");
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}
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}
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/// <summary>
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/// Emits IL for a binary Arithmetic and Logic Unit instruction.
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/// </summary>
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/// <param name="aluOp">Arithmetic and Logic Unit instruction</param>
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/// <param name="opCode">Raw instruction</param>
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/// <exception cref="InvalidOperationException">Throw when the instruction encoding is invalid</exception>
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private void EmitAluOp(AluRegOperation aluOp, int opCode)
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{
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switch (aluOp)
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{
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case AluRegOperation.Add:
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EmitLoadGprA(opCode);
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_ilGen.Emit(OpCodes.Conv_U8);
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EmitLoadGprB(opCode);
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_ilGen.Emit(OpCodes.Conv_U8);
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_ilGen.Emit(OpCodes.Add);
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_ilGen.Emit(OpCodes.Dup);
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_ilGen.Emit(OpCodes.Ldc_I8, 0xffffffffL);
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_ilGen.Emit(OpCodes.Cgt_Un);
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_ilGen.Emit(OpCodes.Stloc, _carry);
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_ilGen.Emit(OpCodes.Conv_U4);
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break;
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case AluRegOperation.AddWithCarry:
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EmitLoadGprA(opCode);
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_ilGen.Emit(OpCodes.Conv_U8);
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EmitLoadGprB(opCode);
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_ilGen.Emit(OpCodes.Conv_U8);
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_ilGen.Emit(OpCodes.Ldloc_S, _carry);
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_ilGen.Emit(OpCodes.Conv_U8);
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_ilGen.Emit(OpCodes.Add);
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_ilGen.Emit(OpCodes.Add);
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_ilGen.Emit(OpCodes.Dup);
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_ilGen.Emit(OpCodes.Ldc_I8, 0xffffffffL);
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_ilGen.Emit(OpCodes.Cgt_Un);
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_ilGen.Emit(OpCodes.Stloc, _carry);
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_ilGen.Emit(OpCodes.Conv_U4);
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break;
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case AluRegOperation.Subtract:
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EmitLoadGprA(opCode);
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_ilGen.Emit(OpCodes.Conv_U8);
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EmitLoadGprB(opCode);
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_ilGen.Emit(OpCodes.Conv_U8);
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_ilGen.Emit(OpCodes.Sub);
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_ilGen.Emit(OpCodes.Dup);
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_ilGen.Emit(OpCodes.Ldc_I8, 0x100000000L);
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_ilGen.Emit(OpCodes.Clt_Un);
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_ilGen.Emit(OpCodes.Stloc, _carry);
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_ilGen.Emit(OpCodes.Conv_U4);
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break;
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case AluRegOperation.SubtractWithBorrow:
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EmitLoadGprA(opCode);
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_ilGen.Emit(OpCodes.Conv_U8);
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EmitLoadGprB(opCode);
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_ilGen.Emit(OpCodes.Conv_U8);
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_ilGen.Emit(OpCodes.Ldc_I4_1);
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_ilGen.Emit(OpCodes.Ldloc_S, _carry);
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_ilGen.Emit(OpCodes.Sub);
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_ilGen.Emit(OpCodes.Conv_U8);
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_ilGen.Emit(OpCodes.Sub);
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_ilGen.Emit(OpCodes.Sub);
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_ilGen.Emit(OpCodes.Dup);
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_ilGen.Emit(OpCodes.Ldc_I8, 0x100000000L);
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_ilGen.Emit(OpCodes.Clt_Un);
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_ilGen.Emit(OpCodes.Stloc, _carry);
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_ilGen.Emit(OpCodes.Conv_U4);
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break;
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case AluRegOperation.BitwiseExclusiveOr:
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EmitLoadGprA(opCode);
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EmitLoadGprB(opCode);
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_ilGen.Emit(OpCodes.Xor);
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break;
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case AluRegOperation.BitwiseOr:
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EmitLoadGprA(opCode);
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EmitLoadGprB(opCode);
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_ilGen.Emit(OpCodes.Or);
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break;
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case AluRegOperation.BitwiseAnd:
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EmitLoadGprA(opCode);
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EmitLoadGprB(opCode);
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_ilGen.Emit(OpCodes.And);
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break;
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case AluRegOperation.BitwiseAndNot:
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EmitLoadGprA(opCode);
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EmitLoadGprB(opCode);
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_ilGen.Emit(OpCodes.Not);
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_ilGen.Emit(OpCodes.And);
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break;
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case AluRegOperation.BitwiseNotAnd:
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EmitLoadGprA(opCode);
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EmitLoadGprB(opCode);
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_ilGen.Emit(OpCodes.And);
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_ilGen.Emit(OpCodes.Not);
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break;
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default:
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throw new InvalidOperationException($"Invalid operation \"{aluOp}\" on instruction 0x{opCode:X8}.");
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}
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}
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/// <summary>
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/// Loads a immediate value on the IL evaluation stack.
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/// </summary>
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/// <param name="opCode">Instruction from where the immediate should be extracted</param>
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private void EmitLoadImm(int opCode)
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{
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// Note: The immediate is signed, the sign-extension is intended here.
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_ilGen.Emit(OpCodes.Ldc_I4, opCode >> 14);
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}
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/// <summary>
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/// Loads a value from the General Purpose register specified as first operand on the IL evaluation stack.
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/// </summary>
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/// <param name="opCode">Instruction from where the register number should be extracted</param>
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private void EmitLoadGprA(int opCode)
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{
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EmitLoadGpr((opCode >> 11) & 7);
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}
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/// <summary>
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/// Loads a value from the General Purpose register specified as second operand on the IL evaluation stack.
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/// </summary>
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/// <param name="opCode">Instruction from where the register number should be extracted</param>
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private void EmitLoadGprB(int opCode)
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{
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EmitLoadGpr((opCode >> 14) & 7);
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}
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/// <summary>
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/// Loads a value a General Purpose register on the IL evaluation stack.
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/// </summary>
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/// <remarks>
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/// Register number 0 has a hardcoded value of 0.
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/// </remarks>
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/// <param name="index">Register number</param>
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private void EmitLoadGpr(int index)
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{
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if (index == 0)
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{
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_ilGen.Emit(OpCodes.Ldc_I4_0);
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}
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else
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{
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_ilGen.Emit(OpCodes.Ldloc_S, _gprs[index]);
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}
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}
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/// <summary>
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/// Emits a call to the method that fetches an argument from the arguments FIFO.
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/// The argument is pushed into the IL evaluation stack.
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/// </summary>
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private void EmitFetchParam()
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{
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_ilGen.Emit(OpCodes.Ldarg_0);
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_ilGen.Emit(OpCodes.Call, typeof(MacroJitContext).GetMethod(nameof(MacroJitContext.FetchParam)));
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}
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/// <summary>
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/// Stores the value on the top of the IL evaluation stack into a General Purpose register.
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/// </summary>
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/// <remarks>
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/// Register number 0 does not exist, reads are hardcoded to 0, and writes are simply discarded.
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/// </remarks>
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/// <param name="opCode">Instruction from where the register number should be extracted</param>
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private void EmitStoreDstGpr(int opCode)
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{
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int index = (opCode >> 8) & 7;
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if (index == 0)
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{
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_ilGen.Emit(OpCodes.Pop);
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}
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else
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{
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_ilGen.Emit(OpCodes.Stloc_S, _gprs[index]);
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}
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}
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/// <summary>
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/// Stores the value on the top of the IL evaluation stack as method address.
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/// This will be used on subsequent send calls as the destination method address.
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/// Additionally, the 6 bits starting at bit 12 will be used as increment value,
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/// added to the method address after each sent value.
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/// </summary>
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private void EmitStoreMethAddr()
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{
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_ilGen.Emit(OpCodes.Dup);
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_ilGen.Emit(OpCodes.Ldc_I4, 0xfff);
|
|
_ilGen.Emit(OpCodes.And);
|
|
_ilGen.Emit(OpCodes.Stloc_S, _methAddr);
|
|
_ilGen.Emit(OpCodes.Ldc_I4, 12);
|
|
_ilGen.Emit(OpCodes.Shr_Un);
|
|
_ilGen.Emit(OpCodes.Ldc_I4, 0x3f);
|
|
_ilGen.Emit(OpCodes.And);
|
|
_ilGen.Emit(OpCodes.Stloc_S, _methIncr);
|
|
}
|
|
|
|
/// <summary>
|
|
/// Sends the value on the top of the IL evaluation stack to the GPU,
|
|
/// using the current method address.
|
|
/// </summary>
|
|
private void EmitSend()
|
|
{
|
|
_ilGen.Emit(OpCodes.Ldarg_1);
|
|
_ilGen.Emit(OpCodes.Ldloc_S, _methAddr);
|
|
_ilGen.Emit(OpCodes.Call, typeof(MacroJitContext).GetMethod(nameof(MacroJitContext.Send)));
|
|
_ilGen.Emit(OpCodes.Ldloc_S, _methAddr);
|
|
_ilGen.Emit(OpCodes.Ldloc_S, _methIncr);
|
|
_ilGen.Emit(OpCodes.Add);
|
|
_ilGen.Emit(OpCodes.Stloc_S, _methAddr);
|
|
}
|
|
}
|
|
}
|