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8a7d99cdea
* Refactoring and optimization on CPU translation * Remove now unused property * Rename ilBlock -> block (local) * Change equality comparison on RegisterMask for consistency Co-Authored-By: gdkchan <gab.dark.100@gmail.com> * Add back the aggressive inlining attribute to the Synchronize method * Implement IEquatable on the Register struct * Fix identation
122 lines
No EOL
3.2 KiB
C#
122 lines
No EOL
3.2 KiB
C#
using ChocolArm64.State;
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using System;
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using System.Collections.Generic;
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using static ChocolArm64.State.RegisterConsts;
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namespace ChocolArm64.IntermediateRepresentation
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{
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class BasicBlock
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{
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public int Index { get; set; }
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public RegisterMask RegInputs { get; private set; }
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public RegisterMask RegOutputs { get; private set; }
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public bool HasStateLoad { get; private set; }
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private List<Operation> _operations;
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public int Count => _operations.Count;
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private BasicBlock _next;
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private BasicBlock _branch;
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public BasicBlock Next
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{
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get => _next;
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set => _next = AddSuccessor(_next, value);
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}
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public BasicBlock Branch
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{
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get => _branch;
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set => _branch = AddSuccessor(_branch, value);
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}
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public List<BasicBlock> Predecessors { get; }
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public BasicBlock(int index = 0)
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{
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Index = index;
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_operations = new List<Operation>();
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Predecessors = new List<BasicBlock>();
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}
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private BasicBlock AddSuccessor(BasicBlock oldBlock, BasicBlock newBlock)
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{
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oldBlock?.Predecessors.Remove(this);
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newBlock?.Predecessors.Add(this);
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return newBlock;
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}
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public void Add(Operation operation)
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{
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if (operation.Type == OperationType.LoadLocal ||
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operation.Type == OperationType.StoreLocal)
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{
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int index = operation.GetArg<int>(0);
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if (IsRegIndex(index))
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{
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long intMask = 0;
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long vecMask = 0;
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switch (operation.GetArg<RegisterType>(1))
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{
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case RegisterType.Flag: intMask = (1L << RegsCount) << index; break;
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case RegisterType.Int: intMask = 1L << index; break;
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case RegisterType.Vector: vecMask = 1L << index; break;
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}
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RegisterMask mask = new RegisterMask(intMask, vecMask);
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if (operation.Type == OperationType.LoadLocal)
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{
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RegInputs |= mask & ~RegOutputs;
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}
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else
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{
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RegOutputs |= mask;
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}
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}
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}
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else if (operation.Type == OperationType.LoadContext)
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{
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HasStateLoad = true;
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}
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operation.Parent = this;
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_operations.Add(operation);
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}
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public static bool IsRegIndex(int index)
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{
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return (uint)index < RegsCount;
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}
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public Operation GetOperation(int index)
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{
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if ((uint)index >= _operations.Count)
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{
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throw new ArgumentOutOfRangeException(nameof(index));
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}
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return _operations[index];
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}
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public Operation GetLastOp()
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{
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if (Count == 0)
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{
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return null;
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}
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return _operations[Count - 1];
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}
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}
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} |