mirror of
https://github.com/ryujinx-mirror/ryujinx.git
synced 2024-12-23 19:25:46 +00:00
a731ab3a2a
* Start of the ARMeilleure project * Refactoring around the old IRAdapter, now renamed to PreAllocator * Optimize the LowestBitSet method * Add CLZ support and fix CLS implementation * Add missing Equals and GetHashCode overrides on some structs, misc small tweaks * Implement the ByteSwap IR instruction, and some refactoring on the assembler * Implement the DivideUI IR instruction and fix 64-bits IDIV * Correct constant operand type on CSINC * Move division instructions implementation to InstEmitDiv * Fix destination type for the ConditionalSelect IR instruction * Implement UMULH and SMULH, with new IR instructions * Fix some issues with shift instructions * Fix constant types for BFM instructions * Fix up new tests using the new V128 struct * Update tests * Move DIV tests to a separate file * Add support for calls, and some instructions that depends on them * Start adding support for SIMD & FP types, along with some of the related ARM instructions * Fix some typos and the divide instruction with FP operands * Fix wrong method call on Clz_V * Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes * Implement SIMD logical instructions and more misc. fixes * Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations * Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes * Implement SIMD shift instruction and fix Dup_V * Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table * Fix check with tolerance on tester * Implement FP & SIMD comparison instructions, and some fixes * Update FCVT (Scalar) encoding on the table to support the Half-float variants * Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes * Use old memory access methods, made a start on SIMD memory insts support, some fixes * Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes * Fix arguments count with struct return values, other fixes * More instructions * Misc. fixes and integrate LDj3SNuD fixes * Update tests * Add a faster linear scan allocator, unwinding support on windows, and other changes * Update Ryujinx.HLE * Update Ryujinx.Graphics * Fix V128 return pointer passing, RCX is clobbered * Update Ryujinx.Tests * Update ITimeZoneService * Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks * Use generic GetFunctionPointerForDelegate method and other tweaks * Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics * Remove some unused code on the assembler * Fix REX.W prefix regression on float conversion instructions, add some sort of profiler * Add hardware capability detection * Fix regression on Sha1h and revert Fcm** changes * Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator * Fix silly mistake introduced on last commit on CpuId * Generate inline stack probes when the stack allocation is too large * Initial support for the System-V ABI * Support multiple destination operands * Fix SSE2 VectorInsert8 path, and other fixes * Change placement of XMM callee save and restore code to match other compilers * Rename Dest to Destination and Inst to Instruction * Fix a regression related to calls and the V128 type * Add an extra space on comments to match code style * Some refactoring * Fix vector insert FP32 SSE2 path * Port over the ARM32 instructions * Avoid memory protection races on JIT Cache * Another fix on VectorInsert FP32 (thanks to LDj3SNuD * Float operands don't need to use the same register when VEX is supported * Add a new register allocator, higher quality code for hot code (tier up), and other tweaks * Some nits, small improvements on the pre allocator * CpuThreadState is gone * Allow changing CPU emulators with a config entry * Add runtime identifiers on the ARMeilleure project * Allow switching between CPUs through a config entry (pt. 2) * Change win10-x64 to win-x64 on projects * Update the Ryujinx project to use ARMeilleure * Ensure that the selected register is valid on the hybrid allocator * Allow exiting on returns to 0 (should fix test regression) * Remove register assignments for most used variables on the hybrid allocator * Do not use fixed registers as spill temp * Add missing namespace and remove unneeded using * Address PR feedback * Fix types, etc * Enable AssumeStrictAbiCompliance by default * Ensure that Spill and Fill don't load or store any more than necessary
693 lines
26 KiB
C#
693 lines
26 KiB
C#
#define SimdIns
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using ARMeilleure.State;
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using NUnit.Framework;
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namespace Ryujinx.Tests.Cpu
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{
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[Category("SimdIns")]
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public sealed class CpuTestSimdIns : CpuTest
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{
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#if SimdIns
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#region "ValueSource"
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private static ulong[] _1D_()
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{
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return new ulong[] { 0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul };
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}
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private static ulong[] _2S_()
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{
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return new ulong[] { 0x0000000000000000ul, 0x7FFFFFFF7FFFFFFFul,
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0x8000000080000000ul, 0xFFFFFFFFFFFFFFFFul };
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}
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private static ulong[] _4H_()
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{
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return new ulong[] { 0x0000000000000000ul, 0x7FFF7FFF7FFF7FFFul,
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0x8000800080008000ul, 0xFFFFFFFFFFFFFFFFul };
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}
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private static ulong[] _8B_()
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{
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return new ulong[] { 0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful,
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0x8080808080808080ul, 0xFFFFFFFFFFFFFFFFul };
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}
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private static ulong[] _8B4H_()
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{
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return new ulong[] { 0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful,
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0x8080808080808080ul, 0x7FFF7FFF7FFF7FFFul,
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0x8000800080008000ul, 0xFFFFFFFFFFFFFFFFul };
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}
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private static ulong[] _8B4H2S_()
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{
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return new ulong[] { 0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful,
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0x8080808080808080ul, 0x7FFF7FFF7FFF7FFFul,
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0x8000800080008000ul, 0x7FFFFFFF7FFFFFFFul,
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0x8000000080000000ul, 0xFFFFFFFFFFFFFFFFul };
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}
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private static uint[] _W_()
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{
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return new uint[] { 0x00000000u, 0x0000007Fu,
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0x00000080u, 0x000000FFu,
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0x00007FFFu, 0x00008000u,
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0x0000FFFFu, 0x7FFFFFFFu,
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0x80000000u, 0xFFFFFFFFu };
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}
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private static ulong[] _X_()
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{
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return new ulong[] { 0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul };
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}
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#endregion
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private const int RndCnt = 2;
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private const int RndCntIndex = 2;
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[Test, Pairwise, Description("DUP <Vd>.<T>, W<n>")]
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public void Dup_Gp_W([Values(0u)] uint rd,
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[Values(1u, 31u)] uint rn,
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[ValueSource("_W_")] [Random(RndCnt)] uint wn,
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[Values(0, 1, 2)] int size, // Q0: <8B, 4H, 2S>
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[Values(0b0u, 0b1u)] uint q) // Q1: <16B, 8H, 4S>
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{
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uint imm5 = (1u << size) & 0x1Fu;
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uint opcode = 0x0E000C00; // RESERVED
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opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
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opcode |= (imm5 << 16);
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opcode |= ((q & 1) << 30);
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uint w31 = TestContext.CurrentContext.Random.NextUInt();
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ulong z = TestContext.CurrentContext.Random.NextULong();
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V128 v0 = MakeVectorE0E1(z, z);
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SingleOpcode(opcode, x1: wn, x31: w31, v0: v0);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("DUP <Vd>.<T>, X<n>")]
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public void Dup_Gp_X([Values(0u)] uint rd,
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[Values(1u, 31u)] uint rn,
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[ValueSource("_X_")] [Random(RndCnt)] ulong xn)
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{
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uint opcode = 0x4E080C00; // DUP V0.2D, X0
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opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
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ulong x31 = TestContext.CurrentContext.Random.NextULong();
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ulong z = TestContext.CurrentContext.Random.NextULong();
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V128 v0 = MakeVectorE0E1(z, z);
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SingleOpcode(opcode, x1: xn, x31: x31, v0: v0);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("DUP B0, V1.B[<index>]")]
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public void Dup_S_B([ValueSource("_8B_")] [Random(RndCnt)] ulong a,
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[Values(0u, 15u)] [Random(1u, 14u, RndCntIndex)] uint index)
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{
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const int size = 0;
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uint imm5 = (index << (size + 1) | 1u << size) & 0x1Fu;
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uint opcode = 0x5E000420; // RESERVED
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opcode |= (imm5 << 16);
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ulong z = TestContext.CurrentContext.Random.NextULong();
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V128 v0 = MakeVectorE0E1(z, z);
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V128 v1 = MakeVectorE0E1(a, a);
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SingleOpcode(opcode, v0: v0, v1: v1);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("DUP H0, V1.H[<index>]")]
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public void Dup_S_H([ValueSource("_4H_")] [Random(RndCnt)] ulong a,
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[Values(0u, 7u)] [Random(1u, 6u, RndCntIndex)] uint index)
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{
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const int size = 1;
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uint imm5 = (index << (size + 1) | 1u << size) & 0x1Fu;
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uint opcode = 0x5E000420; // RESERVED
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opcode |= (imm5 << 16);
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ulong z = TestContext.CurrentContext.Random.NextULong();
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V128 v0 = MakeVectorE0E1(z, z);
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V128 v1 = MakeVectorE0E1(a, a);
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SingleOpcode(opcode, v0: v0, v1: v1);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("DUP S0, V1.S[<index>]")]
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public void Dup_S_S([ValueSource("_2S_")] [Random(RndCnt)] ulong a,
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[Values(0u, 1u, 2u, 3u)] uint index)
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{
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const int size = 2;
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uint imm5 = (index << (size + 1) | 1u << size) & 0x1Fu;
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uint opcode = 0x5E000420; // RESERVED
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opcode |= (imm5 << 16);
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ulong z = TestContext.CurrentContext.Random.NextULong();
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V128 v0 = MakeVectorE0E1(z, z);
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V128 v1 = MakeVectorE0E1(a, a);
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SingleOpcode(opcode, v0: v0, v1: v1);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("DUP D0, V1.D[<index>]")]
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public void Dup_S_D([ValueSource("_1D_")] [Random(RndCnt)] ulong a,
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[Values(0u, 1u)] uint index)
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{
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const int size = 3;
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uint imm5 = (index << (size + 1) | 1u << size) & 0x1Fu;
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uint opcode = 0x5E000420; // RESERVED
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opcode |= (imm5 << 16);
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ulong z = TestContext.CurrentContext.Random.NextULong();
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V128 v0 = MakeVectorE0E1(z, z);
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V128 v1 = MakeVectorE0E1(a, a);
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SingleOpcode(opcode, v0: v0, v1: v1);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("DUP <Vd>.<T>, <Vn>.B[<index>]")]
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public void Dup_V_8B_16B([Values(0u)] uint rd,
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[Values(1u, 0u)] uint rn,
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[ValueSource("_8B_")] [Random(RndCnt)] ulong z,
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[ValueSource("_8B_")] [Random(RndCnt)] ulong a,
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[Values(0u, 15u)] [Random(1u, 14u, RndCntIndex)] uint index,
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[Values(0b0u, 0b1u)] uint q) // <8B, 16B>
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{
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const int size = 0;
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uint imm5 = (index << (size + 1) | 1u << size) & 0x1Fu;
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uint opcode = 0x0E000400; // RESERVED
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opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
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opcode |= (imm5 << 16);
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opcode |= ((q & 1) << 30);
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V128 v0 = MakeVectorE0E1(z, z);
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V128 v1 = MakeVectorE0E1(a, a);
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SingleOpcode(opcode, v0: v0, v1: v1);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("DUP <Vd>.<T>, <Vn>.H[<index>]")]
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public void Dup_V_4H_8H([Values(0u)] uint rd,
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[Values(1u, 0u)] uint rn,
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[ValueSource("_4H_")] [Random(RndCnt)] ulong z,
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[ValueSource("_4H_")] [Random(RndCnt)] ulong a,
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[Values(0u, 7u)] [Random(1u, 6u, RndCntIndex)] uint index,
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[Values(0b0u, 0b1u)] uint q) // <4H, 8H>
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{
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const int size = 1;
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uint imm5 = (index << (size + 1) | 1u << size) & 0x1Fu;
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uint opcode = 0x0E000400; // RESERVED
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opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
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opcode |= (imm5 << 16);
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opcode |= ((q & 1) << 30);
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V128 v0 = MakeVectorE0E1(z, z);
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V128 v1 = MakeVectorE0E1(a, a);
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SingleOpcode(opcode, v0: v0, v1: v1);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("DUP <Vd>.<T>, <Vn>.S[<index>]")]
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public void Dup_V_2S_4S([Values(0u)] uint rd,
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[Values(1u, 0u)] uint rn,
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[ValueSource("_2S_")] [Random(RndCnt)] ulong z,
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[ValueSource("_2S_")] [Random(RndCnt)] ulong a,
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[Values(0u, 1u, 2u, 3u)] uint index,
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[Values(0b0u, 0b1u)] uint q) // <2S, 4S>
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{
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const int size = 2;
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uint imm5 = (index << (size + 1) | 1u << size) & 0x1Fu;
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uint opcode = 0x0E000400; // RESERVED
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opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
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opcode |= (imm5 << 16);
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opcode |= ((q & 1) << 30);
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V128 v0 = MakeVectorE0E1(z, z);
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V128 v1 = MakeVectorE0E1(a, a);
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SingleOpcode(opcode, v0: v0, v1: v1);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("DUP <Vd>.<T>, <Vn>.D[<index>]")]
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public void Dup_V_2D([Values(0u)] uint rd,
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[Values(1u, 0u)] uint rn,
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[ValueSource("_1D_")] [Random(RndCnt)] ulong z,
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[ValueSource("_1D_")] [Random(RndCnt)] ulong a,
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[Values(0u, 1u)] uint index,
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[Values(0b1u)] uint q) // <2D>
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{
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const int size = 3;
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uint imm5 = (index << (size + 1) | 1u << size) & 0x1Fu;
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uint opcode = 0x0E000400; // RESERVED
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opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
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opcode |= (imm5 << 16);
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opcode |= ((q & 1) << 30);
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V128 v0 = MakeVectorE0E1(z, z);
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V128 v1 = MakeVectorE0E1(a, a);
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SingleOpcode(opcode, v0: v0, v1: v1);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("INS <Vd>.B[<index>], W<n>")]
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public void Ins_Gp_WB([Values(0u)] uint rd,
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[Values(1u, 31u)] uint rn,
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[ValueSource("_8B_")] [Random(RndCnt)] ulong z,
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[ValueSource("_W_")] [Random(RndCnt)] uint wn,
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[Values(0u, 15u)] [Random(1u, 14u, RndCntIndex)] uint index)
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{
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const int size = 0;
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uint imm5 = (index << (size + 1) | 1u << size) & 0x1Fu;
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uint opcode = 0x4E001C00; // RESERVED
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opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
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opcode |= (imm5 << 16);
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uint w31 = TestContext.CurrentContext.Random.NextUInt();
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V128 v0 = MakeVectorE0E1(z, z);
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SingleOpcode(opcode, x1: wn, x31: w31, v0: v0);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("INS <Vd>.H[<index>], W<n>")]
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public void Ins_Gp_WH([Values(0u)] uint rd,
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[Values(1u, 31u)] uint rn,
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[ValueSource("_4H_")] [Random(RndCnt)] ulong z,
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[ValueSource("_W_")] [Random(RndCnt)] uint wn,
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[Values(0u, 7u)] [Random(1u, 6u, RndCntIndex)] uint index)
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{
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const int size = 1;
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uint imm5 = (index << (size + 1) | 1u << size) & 0x1Fu;
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uint opcode = 0x4E001C00; // RESERVED
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opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
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opcode |= (imm5 << 16);
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uint w31 = TestContext.CurrentContext.Random.NextUInt();
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V128 v0 = MakeVectorE0E1(z, z);
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SingleOpcode(opcode, x1: wn, x31: w31, v0: v0);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("INS <Vd>.S[<index>], W<n>")]
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public void Ins_Gp_WS([Values(0u)] uint rd,
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[Values(1u, 31u)] uint rn,
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[ValueSource("_2S_")] [Random(RndCnt)] ulong z,
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[ValueSource("_W_")] [Random(RndCnt)] uint wn,
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[Values(0u, 1u, 2u, 3u)] uint index)
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{
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const int size = 2;
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uint imm5 = (index << (size + 1) | 1u << size) & 0x1Fu;
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uint opcode = 0x4E001C00; // RESERVED
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opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
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opcode |= (imm5 << 16);
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uint w31 = TestContext.CurrentContext.Random.NextUInt();
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V128 v0 = MakeVectorE0E1(z, z);
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SingleOpcode(opcode, x1: wn, x31: w31, v0: v0);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("INS <Vd>.D[<index>], X<n>")]
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public void Ins_Gp_XD([Values(0u)] uint rd,
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[Values(1u, 31u)] uint rn,
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[ValueSource("_1D_")] [Random(RndCnt)] ulong z,
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[ValueSource("_X_")] [Random(RndCnt)] ulong xn,
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[Values(0u, 1u)] uint index)
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{
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const int size = 3;
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uint imm5 = (index << (size + 1) | 1u << size) & 0x1Fu;
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uint opcode = 0x4E001C00; // RESERVED
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opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
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opcode |= (imm5 << 16);
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ulong x31 = TestContext.CurrentContext.Random.NextULong();
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V128 v0 = MakeVectorE0E1(z, z);
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SingleOpcode(opcode, x1: xn, x31: x31, v0: v0);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("INS <Vd>.B[<index1>], <Vn>.B[<index2>]")]
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public void Ins_V_BB([Values(0u)] uint rd,
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[Values(1u, 0u)] uint rn,
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[ValueSource("_8B_")] [Random(RndCnt)] ulong z,
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[ValueSource("_8B_")] [Random(RndCnt)] ulong a,
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[Values(0u, 15u)] [Random(1u, 14u, RndCntIndex)] uint dstIndex,
|
|
[Values(0u, 15u)] [Random(1u, 14u, RndCntIndex)] uint srcIndex)
|
|
{
|
|
const int size = 0;
|
|
|
|
uint imm5 = (dstIndex << (size + 1) | 1u << size) & 0x1Fu;
|
|
uint imm4 = (srcIndex << size) & 0xFu;
|
|
|
|
uint opcode = 0x6E000400; // RESERVED
|
|
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
|
|
opcode |= (imm5 << 16);
|
|
opcode |= (imm4 << 11);
|
|
|
|
V128 v0 = MakeVectorE0E1(z, z);
|
|
V128 v1 = MakeVectorE0E1(a, a);
|
|
|
|
SingleOpcode(opcode, v0: v0, v1: v1);
|
|
|
|
CompareAgainstUnicorn();
|
|
}
|
|
|
|
[Test, Pairwise, Description("INS <Vd>.H[<index1>], <Vn>.H[<index2>]")]
|
|
public void Ins_V_HH([Values(0u)] uint rd,
|
|
[Values(1u, 0u)] uint rn,
|
|
[ValueSource("_4H_")] [Random(RndCnt)] ulong z,
|
|
[ValueSource("_4H_")] [Random(RndCnt)] ulong a,
|
|
[Values(0u, 7u)] [Random(1u, 6u, RndCntIndex)] uint dstIndex,
|
|
[Values(0u, 7u)] [Random(1u, 6u, RndCntIndex)] uint srcIndex)
|
|
{
|
|
const int size = 1;
|
|
|
|
uint imm5 = (dstIndex << (size + 1) | 1u << size) & 0x1Fu;
|
|
uint imm4 = (srcIndex << size) & 0xFu;
|
|
|
|
uint opcode = 0x6E000400; // RESERVED
|
|
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
|
|
opcode |= (imm5 << 16);
|
|
opcode |= (imm4 << 11);
|
|
|
|
V128 v0 = MakeVectorE0E1(z, z);
|
|
V128 v1 = MakeVectorE0E1(a, a);
|
|
|
|
SingleOpcode(opcode, v0: v0, v1: v1);
|
|
|
|
CompareAgainstUnicorn();
|
|
}
|
|
|
|
[Test, Pairwise, Description("INS <Vd>.S[<index1>], <Vn>.S[<index2>]")]
|
|
public void Ins_V_SS([Values(0u)] uint rd,
|
|
[Values(1u, 0u)] uint rn,
|
|
[ValueSource("_2S_")] [Random(RndCnt)] ulong z,
|
|
[ValueSource("_2S_")] [Random(RndCnt)] ulong a,
|
|
[Values(0u, 1u, 2u, 3u)] uint dstIndex,
|
|
[Values(0u, 1u, 2u, 3u)] uint srcIndex)
|
|
{
|
|
const int size = 2;
|
|
|
|
uint imm5 = (dstIndex << (size + 1) | 1u << size) & 0x1Fu;
|
|
uint imm4 = (srcIndex << size) & 0xFu;
|
|
|
|
uint opcode = 0x6E000400; // RESERVED
|
|
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
|
|
opcode |= (imm5 << 16);
|
|
opcode |= (imm4 << 11);
|
|
|
|
V128 v0 = MakeVectorE0E1(z, z);
|
|
V128 v1 = MakeVectorE0E1(a, a);
|
|
|
|
SingleOpcode(opcode, v0: v0, v1: v1);
|
|
|
|
CompareAgainstUnicorn();
|
|
}
|
|
|
|
[Test, Pairwise, Description("INS <Vd>.D[<index1>], <Vn>.D[<index2>]")]
|
|
public void Ins_V_DD([Values(0u)] uint rd,
|
|
[Values(1u, 0u)] uint rn,
|
|
[ValueSource("_1D_")] [Random(RndCnt)] ulong z,
|
|
[ValueSource("_1D_")] [Random(RndCnt)] ulong a,
|
|
[Values(0u, 1u)] uint dstIndex,
|
|
[Values(0u, 1u)] uint srcIndex)
|
|
{
|
|
const int size = 3;
|
|
|
|
uint imm5 = (dstIndex << (size + 1) | 1u << size) & 0x1Fu;
|
|
uint imm4 = (srcIndex << size) & 0xFu;
|
|
|
|
uint opcode = 0x6E000400; // RESERVED
|
|
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
|
|
opcode |= (imm5 << 16);
|
|
opcode |= (imm4 << 11);
|
|
|
|
V128 v0 = MakeVectorE0E1(z, z);
|
|
V128 v1 = MakeVectorE0E1(a, a);
|
|
|
|
SingleOpcode(opcode, v0: v0, v1: v1);
|
|
|
|
CompareAgainstUnicorn();
|
|
}
|
|
|
|
[Test, Pairwise, Description("SMOV <Wd>, <Vn>.B[<index>]")]
|
|
public void Smov_S_BW([Values(0u, 31u)] uint rd,
|
|
[Values(1u)] uint rn,
|
|
[ValueSource("_8B_")] [Random(RndCnt)] ulong a,
|
|
[Values(0u, 15u)] [Random(1u, 14u, RndCntIndex)] uint index)
|
|
{
|
|
const int size = 0;
|
|
|
|
uint imm5 = (index << (size + 1) | 1u << size) & 0x1Fu;
|
|
|
|
uint opcode = 0x0E002C00; // RESERVED
|
|
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
|
|
opcode |= (imm5 << 16);
|
|
|
|
ulong x0 = (ulong)TestContext.CurrentContext.Random.NextUInt() << 32;
|
|
uint w31 = TestContext.CurrentContext.Random.NextUInt();
|
|
V128 v1 = MakeVectorE0E1(a, a);
|
|
|
|
SingleOpcode(opcode, x0: x0, x31: w31, v1: v1);
|
|
|
|
CompareAgainstUnicorn();
|
|
}
|
|
|
|
[Test, Pairwise, Description("SMOV <Wd>, <Vn>.H[<index>]")]
|
|
public void Smov_S_HW([Values(0u, 31u)] uint rd,
|
|
[Values(1u)] uint rn,
|
|
[ValueSource("_4H_")] [Random(RndCnt)] ulong a,
|
|
[Values(0u, 7u)] [Random(1u, 6u, RndCntIndex)] uint index)
|
|
{
|
|
const int size = 1;
|
|
|
|
uint imm5 = (index << (size + 1) | 1u << size) & 0x1Fu;
|
|
|
|
uint opcode = 0x0E002C00; // RESERVED
|
|
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
|
|
opcode |= (imm5 << 16);
|
|
|
|
ulong x0 = (ulong)TestContext.CurrentContext.Random.NextUInt() << 32;
|
|
uint w31 = TestContext.CurrentContext.Random.NextUInt();
|
|
V128 v1 = MakeVectorE0E1(a, a);
|
|
|
|
SingleOpcode(opcode, x0: x0, x31: w31, v1: v1);
|
|
|
|
CompareAgainstUnicorn();
|
|
}
|
|
|
|
[Test, Pairwise, Description("SMOV <Xd>, <Vn>.B[<index>]")]
|
|
public void Smov_S_BX([Values(0u, 31u)] uint rd,
|
|
[Values(1u)] uint rn,
|
|
[ValueSource("_8B_")] [Random(RndCnt)] ulong a,
|
|
[Values(0u, 15u)] [Random(1u, 14u, RndCntIndex)] uint index)
|
|
{
|
|
const int size = 0;
|
|
|
|
uint imm5 = (index << (size + 1) | 1u << size) & 0x1Fu;
|
|
|
|
uint opcode = 0x4E002C00; // RESERVED
|
|
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
|
|
opcode |= (imm5 << 16);
|
|
|
|
ulong x31 = TestContext.CurrentContext.Random.NextULong();
|
|
V128 v1 = MakeVectorE0E1(a, a);
|
|
|
|
SingleOpcode(opcode, x31: x31, v1: v1);
|
|
|
|
CompareAgainstUnicorn();
|
|
}
|
|
|
|
[Test, Pairwise, Description("SMOV <Xd>, <Vn>.H[<index>]")]
|
|
public void Smov_S_HX([Values(0u, 31u)] uint rd,
|
|
[Values(1u)] uint rn,
|
|
[ValueSource("_4H_")] [Random(RndCnt)] ulong a,
|
|
[Values(0u, 7u)] [Random(1u, 6u, RndCntIndex)] uint index)
|
|
{
|
|
const int size = 1;
|
|
|
|
uint imm5 = (index << (size + 1) | 1u << size) & 0x1Fu;
|
|
|
|
uint opcode = 0x4E002C00; // RESERVED
|
|
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
|
|
opcode |= (imm5 << 16);
|
|
|
|
ulong x31 = TestContext.CurrentContext.Random.NextULong();
|
|
V128 v1 = MakeVectorE0E1(a, a);
|
|
|
|
SingleOpcode(opcode, x31: x31, v1: v1);
|
|
|
|
CompareAgainstUnicorn();
|
|
}
|
|
|
|
[Test, Pairwise, Description("SMOV <Xd>, <Vn>.S[<index>]")]
|
|
public void Smov_S_SX([Values(0u, 31u)] uint rd,
|
|
[Values(1u)] uint rn,
|
|
[ValueSource("_2S_")] [Random(RndCnt)] ulong a,
|
|
[Values(0u, 1u, 2u, 3u)] uint index)
|
|
{
|
|
const int size = 2;
|
|
|
|
uint imm5 = (index << (size + 1) | 1u << size) & 0x1Fu;
|
|
|
|
uint opcode = 0x4E002C00; // RESERVED
|
|
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
|
|
opcode |= (imm5 << 16);
|
|
|
|
ulong x31 = TestContext.CurrentContext.Random.NextULong();
|
|
V128 v1 = MakeVectorE0E1(a, a);
|
|
|
|
SingleOpcode(opcode, x31: x31, v1: v1);
|
|
|
|
CompareAgainstUnicorn();
|
|
}
|
|
|
|
[Test, Pairwise, Description("UMOV <Wd>, <Vn>.B[<index>]")]
|
|
public void Umov_S_BW([Values(0u, 31u)] uint rd,
|
|
[Values(1u)] uint rn,
|
|
[ValueSource("_8B_")] [Random(RndCnt)] ulong a,
|
|
[Values(0u, 15u)] [Random(1u, 14u, RndCntIndex)] uint index)
|
|
{
|
|
const int size = 0;
|
|
|
|
uint imm5 = (index << (size + 1) | 1u << size) & 0x1Fu;
|
|
|
|
uint opcode = 0x0E003C00; // RESERVED
|
|
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
|
|
opcode |= (imm5 << 16);
|
|
|
|
ulong x0 = (ulong)TestContext.CurrentContext.Random.NextUInt() << 32;
|
|
uint w31 = TestContext.CurrentContext.Random.NextUInt();
|
|
V128 v1 = MakeVectorE0E1(a, a);
|
|
|
|
SingleOpcode(opcode, x0: x0, x31: w31, v1: v1);
|
|
|
|
CompareAgainstUnicorn();
|
|
}
|
|
|
|
[Test, Pairwise, Description("UMOV <Wd>, <Vn>.H[<index>]")]
|
|
public void Umov_S_HW([Values(0u, 31u)] uint rd,
|
|
[Values(1u)] uint rn,
|
|
[ValueSource("_4H_")] [Random(RndCnt)] ulong a,
|
|
[Values(0u, 7u)] [Random(1u, 6u, RndCntIndex)] uint index)
|
|
{
|
|
const int size = 1;
|
|
|
|
uint imm5 = (index << (size + 1) | 1u << size) & 0x1Fu;
|
|
|
|
uint opcode = 0x0E003C00; // RESERVED
|
|
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
|
|
opcode |= (imm5 << 16);
|
|
|
|
ulong x0 = (ulong)TestContext.CurrentContext.Random.NextUInt() << 32;
|
|
uint w31 = TestContext.CurrentContext.Random.NextUInt();
|
|
V128 v1 = MakeVectorE0E1(a, a);
|
|
|
|
SingleOpcode(opcode, x0: x0, x31: w31, v1: v1);
|
|
|
|
CompareAgainstUnicorn();
|
|
}
|
|
|
|
[Test, Pairwise, Description("UMOV <Wd>, <Vn>.S[<index>]")]
|
|
public void Umov_S_SW([Values(0u, 31u)] uint rd,
|
|
[Values(1u)] uint rn,
|
|
[ValueSource("_2S_")] [Random(RndCnt)] ulong a,
|
|
[Values(0u, 1u, 2u, 3u)] uint index)
|
|
{
|
|
const int size = 2;
|
|
|
|
uint imm5 = (index << (size + 1) | 1u << size) & 0x1Fu;
|
|
|
|
uint opcode = 0x0E003C00; // RESERVED
|
|
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
|
|
opcode |= (imm5 << 16);
|
|
|
|
ulong x0 = (ulong)TestContext.CurrentContext.Random.NextUInt() << 32;
|
|
uint w31 = TestContext.CurrentContext.Random.NextUInt();
|
|
V128 v1 = MakeVectorE0E1(a, a);
|
|
|
|
SingleOpcode(opcode, x0: x0, x31: w31, v1: v1);
|
|
|
|
CompareAgainstUnicorn();
|
|
}
|
|
|
|
[Test, Pairwise, Description("UMOV <Xd>, <Vn>.D[<index>]")]
|
|
public void Umov_S_DX([Values(0u, 31u)] uint rd,
|
|
[Values(1u)] uint rn,
|
|
[ValueSource("_1D_")] [Random(RndCnt)] ulong a,
|
|
[Values(0u, 1u)] uint index)
|
|
{
|
|
const int size = 3;
|
|
|
|
uint imm5 = (index << (size + 1) | 1u << size) & 0x1Fu;
|
|
|
|
uint opcode = 0x4E003C00; // RESERVED
|
|
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
|
|
opcode |= (imm5 << 16);
|
|
|
|
ulong x31 = TestContext.CurrentContext.Random.NextULong();
|
|
V128 v1 = MakeVectorE0E1(a, a);
|
|
|
|
SingleOpcode(opcode, x31: x31, v1: v1);
|
|
|
|
CompareAgainstUnicorn();
|
|
}
|
|
#endif
|
|
}
|
|
}
|