mirror of
https://github.com/ryujinx-mirror/ryujinx.git
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e674b37710
* Update CpuTest.cs * Update CpuTestSimd.cs * Superseded. * Update AInstEmitSimdCvt.cs * Update ASoftFloat.cs * Nit. * Update PackageReferences. * Update AInstEmitSimdArithmetic.cs * Update AVectorHelper.cs * Update ASoftFloat.cs * Update ASoftFallback.cs * Update AThreadState.cs * Create FPType.cs * Create FPExc.cs * Create FPCR.cs * Create FPSR.cs * Update ARoundMode.cs * Update APState.cs * Avoid an unwanted implicit cast of the operator >= to long, continuing to check for negative values. Remove a leftover. * Nits.
2127 lines
65 KiB
C#
2127 lines
65 KiB
C#
using ChocolArm64.State;
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using System;
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using System.Diagnostics;
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using System.Runtime.CompilerServices;
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namespace ChocolArm64.Instruction
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{
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static class ASoftFloat
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{
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static ASoftFloat()
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{
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RecipEstimateTable = BuildRecipEstimateTable();
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InvSqrtEstimateTable = BuildInvSqrtEstimateTable();
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}
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private static readonly byte[] RecipEstimateTable;
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private static readonly byte[] InvSqrtEstimateTable;
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private static byte[] BuildRecipEstimateTable()
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{
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byte[] Table = new byte[256];
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for (ulong index = 0; index < 256; index++)
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{
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ulong a = index | 0x100;
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a = (a << 1) + 1;
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ulong b = 0x80000 / a;
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b = (b + 1) >> 1;
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Table[index] = (byte)(b & 0xFF);
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}
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return Table;
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}
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private static byte[] BuildInvSqrtEstimateTable()
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{
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byte[] Table = new byte[512];
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for (ulong index = 128; index < 512; index++)
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{
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ulong a = index;
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if (a < 256)
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{
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a = (a << 1) + 1;
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}
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else
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{
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a = (a | 1) << 1;
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}
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ulong b = 256;
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while (a * (b + 1) * (b + 1) < (1ul << 28))
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{
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b++;
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}
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b = (b + 1) >> 1;
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Table[index] = (byte)(b & 0xFF);
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}
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return Table;
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}
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[MethodImpl(MethodImplOptions.AggressiveInlining)]
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public static float RecipEstimate(float x)
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{
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return (float)RecipEstimate((double)x);
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}
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public static double RecipEstimate(double x)
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{
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ulong x_bits = (ulong)BitConverter.DoubleToInt64Bits(x);
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ulong x_sign = x_bits & 0x8000000000000000;
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ulong x_exp = (x_bits >> 52) & 0x7FF;
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ulong scaled = x_bits & ((1ul << 52) - 1);
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if (x_exp >= 2045)
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{
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if (x_exp == 0x7ff && scaled != 0)
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{
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// NaN
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return BitConverter.Int64BitsToDouble((long)(x_bits | 0x0008000000000000));
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}
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// Infinity, or Out of range -> Zero
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return BitConverter.Int64BitsToDouble((long)x_sign);
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}
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if (x_exp == 0)
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{
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if (scaled == 0)
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{
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// Zero -> Infinity
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return BitConverter.Int64BitsToDouble((long)(x_sign | 0x7FF0000000000000));
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}
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// Denormal
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if ((scaled & (1ul << 51)) == 0)
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{
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x_exp = ~0ul;
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scaled <<= 2;
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}
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else
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{
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scaled <<= 1;
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}
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}
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scaled >>= 44;
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scaled &= 0xFF;
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ulong result_exp = (2045 - x_exp) & 0x7FF;
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ulong estimate = (ulong)RecipEstimateTable[scaled];
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ulong fraction = estimate << 44;
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if (result_exp == 0)
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{
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fraction >>= 1;
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fraction |= 1ul << 51;
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}
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else if (result_exp == 0x7FF)
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{
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result_exp = 0;
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fraction >>= 2;
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fraction |= 1ul << 50;
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}
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ulong result = x_sign | (result_exp << 52) | fraction;
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return BitConverter.Int64BitsToDouble((long)result);
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}
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[MethodImpl(MethodImplOptions.AggressiveInlining)]
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public static float InvSqrtEstimate(float x)
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{
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return (float)InvSqrtEstimate((double)x);
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}
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public static double InvSqrtEstimate(double x)
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{
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ulong x_bits = (ulong)BitConverter.DoubleToInt64Bits(x);
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ulong x_sign = x_bits & 0x8000000000000000;
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long x_exp = (long)((x_bits >> 52) & 0x7FF);
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ulong scaled = x_bits & ((1ul << 52) - 1);
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if (x_exp == 0x7FF && scaled != 0)
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{
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// NaN
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return BitConverter.Int64BitsToDouble((long)(x_bits | 0x0008000000000000));
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}
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if (x_exp == 0)
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{
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if (scaled == 0)
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{
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// Zero -> Infinity
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return BitConverter.Int64BitsToDouble((long)(x_sign | 0x7FF0000000000000));
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}
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// Denormal
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while ((scaled & (1 << 51)) == 0)
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{
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scaled <<= 1;
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x_exp--;
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}
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scaled <<= 1;
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}
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if (x_sign != 0)
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{
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// Negative -> NaN
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return BitConverter.Int64BitsToDouble((long)0x7FF8000000000000);
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}
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if (x_exp == 0x7ff && scaled == 0)
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{
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// Infinity -> Zero
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return BitConverter.Int64BitsToDouble((long)x_sign);
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}
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if (((ulong)x_exp & 1) == 1)
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{
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scaled >>= 45;
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scaled &= 0xFF;
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scaled |= 0x80;
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}
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else
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{
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scaled >>= 44;
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scaled &= 0xFF;
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scaled |= 0x100;
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}
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ulong result_exp = ((ulong)(3068 - x_exp) / 2) & 0x7FF;
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ulong estimate = (ulong)InvSqrtEstimateTable[scaled];
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ulong fraction = estimate << 44;
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ulong result = x_sign | (result_exp << 52) | fraction;
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return BitConverter.Int64BitsToDouble((long)result);
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}
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}
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static class ASoftFloat16_32
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{
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public static float FPConvert(ushort ValueBits, AThreadState State)
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{
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Debug.WriteLineIf(State.Fpcr != 0, $"ASoftFloat16_32.FPConvert: State.Fpcr = 0x{State.Fpcr:X8}");
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double Real = ValueBits.FPUnpackCV(out FPType Type, out bool Sign, State);
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float Result;
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if (Type == FPType.SNaN || Type == FPType.QNaN)
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{
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if (State.GetFpcrFlag(FPCR.DN))
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{
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Result = FPDefaultNaN();
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}
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else
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{
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Result = FPConvertNaN(ValueBits);
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}
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if (Type == FPType.SNaN)
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{
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FPProcessException(FPExc.InvalidOp, State);
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}
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}
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else if (Type == FPType.Infinity)
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{
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Result = FPInfinity(Sign);
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}
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else if (Type == FPType.Zero)
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{
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Result = FPZero(Sign);
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}
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else
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{
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Result = FPRoundCV(Real, State);
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}
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return Result;
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}
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private static float FPDefaultNaN()
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{
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return -float.NaN;
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}
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private static float FPInfinity(bool Sign)
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{
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return Sign ? float.NegativeInfinity : float.PositiveInfinity;
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}
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private static float FPZero(bool Sign)
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{
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return Sign ? -0f : +0f;
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}
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private static float FPMaxNormal(bool Sign)
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{
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return Sign ? float.MinValue : float.MaxValue;
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}
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private static double FPUnpackCV(this ushort ValueBits, out FPType Type, out bool Sign, AThreadState State)
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{
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Sign = (~(uint)ValueBits & 0x8000u) == 0u;
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uint Exp16 = ((uint)ValueBits & 0x7C00u) >> 10;
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uint Frac16 = (uint)ValueBits & 0x03FFu;
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double Real;
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if (Exp16 == 0u)
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{
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if (Frac16 == 0u)
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{
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Type = FPType.Zero;
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Real = 0d;
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}
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else
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{
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Type = FPType.Nonzero; // Subnormal.
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Real = Math.Pow(2d, -14) * ((double)Frac16 * Math.Pow(2d, -10));
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}
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}
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else if (Exp16 == 0x1Fu && !State.GetFpcrFlag(FPCR.AHP))
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{
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if (Frac16 == 0u)
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{
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Type = FPType.Infinity;
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Real = Math.Pow(2d, 1000);
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}
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else
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{
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Type = (~Frac16 & 0x0200u) == 0u ? FPType.QNaN : FPType.SNaN;
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Real = 0d;
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}
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}
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else
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{
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Type = FPType.Nonzero; // Normal.
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Real = Math.Pow(2d, (int)Exp16 - 15) * (1d + (double)Frac16 * Math.Pow(2d, -10));
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}
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return Sign ? -Real : Real;
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}
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private static float FPRoundCV(double Real, AThreadState State)
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{
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const int MinimumExp = -126;
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const int E = 8;
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const int F = 23;
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bool Sign;
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double Mantissa;
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if (Real < 0d)
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{
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Sign = true;
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Mantissa = -Real;
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}
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else
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{
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Sign = false;
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Mantissa = Real;
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}
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int Exponent = 0;
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while (Mantissa < 1d)
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{
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Mantissa *= 2d;
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Exponent--;
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}
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while (Mantissa >= 2d)
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{
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Mantissa /= 2d;
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Exponent++;
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}
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if (State.GetFpcrFlag(FPCR.FZ) && Exponent < MinimumExp)
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{
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State.SetFpsrFlag(FPSR.UFC);
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return FPZero(Sign);
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}
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uint BiasedExp = (uint)Math.Max(Exponent - MinimumExp + 1, 0);
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if (BiasedExp == 0u)
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{
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Mantissa /= Math.Pow(2d, MinimumExp - Exponent);
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}
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uint IntMant = (uint)Math.Floor(Mantissa * Math.Pow(2d, F));
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double Error = Mantissa * Math.Pow(2d, F) - (double)IntMant;
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if (BiasedExp == 0u && (Error != 0d || State.GetFpcrFlag(FPCR.UFE)))
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{
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FPProcessException(FPExc.Underflow, State);
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}
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bool OverflowToInf;
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bool RoundUp;
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switch (State.FPRoundingMode())
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{
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default:
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case ARoundMode.ToNearest:
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RoundUp = (Error > 0.5d || (Error == 0.5d && (IntMant & 1u) == 1u));
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OverflowToInf = true;
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break;
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case ARoundMode.TowardsPlusInfinity:
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RoundUp = (Error != 0d && !Sign);
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OverflowToInf = !Sign;
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break;
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case ARoundMode.TowardsMinusInfinity:
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RoundUp = (Error != 0d && Sign);
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OverflowToInf = Sign;
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break;
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case ARoundMode.TowardsZero:
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RoundUp = false;
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OverflowToInf = false;
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break;
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}
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if (RoundUp)
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{
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IntMant++;
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if (IntMant == (uint)Math.Pow(2d, F))
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{
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BiasedExp = 1u;
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}
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if (IntMant == (uint)Math.Pow(2d, F + 1))
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{
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BiasedExp++;
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IntMant >>= 1;
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}
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}
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float Result;
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if (BiasedExp >= (uint)Math.Pow(2d, E) - 1u)
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{
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Result = OverflowToInf ? FPInfinity(Sign) : FPMaxNormal(Sign);
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FPProcessException(FPExc.Overflow, State);
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Error = 1d;
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}
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else
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{
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Result = BitConverter.Int32BitsToSingle(
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(int)((Sign ? 1u : 0u) << 31 | (BiasedExp & 0xFFu) << 23 | (IntMant & 0x007FFFFFu)));
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}
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if (Error != 0d)
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{
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FPProcessException(FPExc.Inexact, State);
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}
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return Result;
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}
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private static float FPConvertNaN(ushort ValueBits)
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{
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return BitConverter.Int32BitsToSingle(
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(int)(((uint)ValueBits & 0x8000u) << 16 | 0x7FC00000u | ((uint)ValueBits & 0x01FFu) << 13));
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}
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private static void FPProcessException(FPExc Exc, AThreadState State)
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{
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int Enable = (int)Exc + 8;
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if ((State.Fpcr & (1 << Enable)) != 0)
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{
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throw new NotImplementedException("floating-point trap handling");
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}
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else
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{
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State.Fpsr |= 1 << (int)Exc;
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}
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}
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}
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static class ASoftFloat32_16
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{
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public static ushort FPConvert(float Value, AThreadState State)
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{
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Debug.WriteLineIf(State.Fpcr != 0, $"ASoftFloat32_16.FPConvert: State.Fpcr = 0x{State.Fpcr:X8}");
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double Real = Value.FPUnpackCV(out FPType Type, out bool Sign, State, out uint ValueBits);
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bool AltHp = State.GetFpcrFlag(FPCR.AHP);
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ushort ResultBits;
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if (Type == FPType.SNaN || Type == FPType.QNaN)
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{
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if (AltHp)
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{
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ResultBits = FPZero(Sign);
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}
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else if (State.GetFpcrFlag(FPCR.DN))
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{
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ResultBits = FPDefaultNaN();
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}
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else
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{
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ResultBits = FPConvertNaN(ValueBits);
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}
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if (Type == FPType.SNaN || AltHp)
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{
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FPProcessException(FPExc.InvalidOp, State);
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}
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}
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else if (Type == FPType.Infinity)
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{
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if (AltHp)
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{
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ResultBits = (ushort)((Sign ? 1u : 0u) << 15 | 0x7FFFu);
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FPProcessException(FPExc.InvalidOp, State);
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}
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else
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{
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ResultBits = FPInfinity(Sign);
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}
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}
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else if (Type == FPType.Zero)
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{
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ResultBits = FPZero(Sign);
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}
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else
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{
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ResultBits = FPRoundCV(Real, State);
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}
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return ResultBits;
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}
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private static ushort FPDefaultNaN()
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{
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return (ushort)0x7E00u;
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}
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private static ushort FPInfinity(bool Sign)
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{
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return Sign ? (ushort)0xFC00u : (ushort)0x7C00u;
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}
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private static ushort FPZero(bool Sign)
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{
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return Sign ? (ushort)0x8000u : (ushort)0x0000u;
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}
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private static ushort FPMaxNormal(bool Sign)
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{
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return Sign ? (ushort)0xFBFFu : (ushort)0x7BFFu;
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}
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private static double FPUnpackCV(this float Value, out FPType Type, out bool Sign, AThreadState State, out uint ValueBits)
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{
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ValueBits = (uint)BitConverter.SingleToInt32Bits(Value);
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Sign = (~ValueBits & 0x80000000u) == 0u;
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uint Exp32 = (ValueBits & 0x7F800000u) >> 23;
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uint Frac32 = ValueBits & 0x007FFFFFu;
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double Real;
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if (Exp32 == 0u)
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{
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if (Frac32 == 0u || State.GetFpcrFlag(FPCR.FZ))
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{
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Type = FPType.Zero;
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Real = 0d;
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if (Frac32 != 0u) FPProcessException(FPExc.InputDenorm, State);
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}
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else
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{
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Type = FPType.Nonzero; // Subnormal.
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Real = Math.Pow(2d, -126) * ((double)Frac32 * Math.Pow(2d, -23));
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}
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}
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else if (Exp32 == 0xFFu)
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{
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if (Frac32 == 0u)
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{
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Type = FPType.Infinity;
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Real = Math.Pow(2d, 1000);
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}
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else
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{
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Type = (~Frac32 & 0x00400000u) == 0u ? FPType.QNaN : FPType.SNaN;
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Real = 0d;
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}
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}
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else
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{
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Type = FPType.Nonzero; // Normal.
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Real = Math.Pow(2d, (int)Exp32 - 127) * (1d + (double)Frac32 * Math.Pow(2d, -23));
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}
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return Sign ? -Real : Real;
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}
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|
|
private static ushort FPRoundCV(double Real, AThreadState State)
|
|
{
|
|
const int MinimumExp = -14;
|
|
|
|
const int E = 5;
|
|
const int F = 10;
|
|
|
|
bool Sign;
|
|
double Mantissa;
|
|
|
|
if (Real < 0d)
|
|
{
|
|
Sign = true;
|
|
Mantissa = -Real;
|
|
}
|
|
else
|
|
{
|
|
Sign = false;
|
|
Mantissa = Real;
|
|
}
|
|
|
|
int Exponent = 0;
|
|
|
|
while (Mantissa < 1d)
|
|
{
|
|
Mantissa *= 2d;
|
|
Exponent--;
|
|
}
|
|
|
|
while (Mantissa >= 2d)
|
|
{
|
|
Mantissa /= 2d;
|
|
Exponent++;
|
|
}
|
|
|
|
uint BiasedExp = (uint)Math.Max(Exponent - MinimumExp + 1, 0);
|
|
|
|
if (BiasedExp == 0u)
|
|
{
|
|
Mantissa /= Math.Pow(2d, MinimumExp - Exponent);
|
|
}
|
|
|
|
uint IntMant = (uint)Math.Floor(Mantissa * Math.Pow(2d, F));
|
|
double Error = Mantissa * Math.Pow(2d, F) - (double)IntMant;
|
|
|
|
if (BiasedExp == 0u && (Error != 0d || State.GetFpcrFlag(FPCR.UFE)))
|
|
{
|
|
FPProcessException(FPExc.Underflow, State);
|
|
}
|
|
|
|
bool OverflowToInf;
|
|
bool RoundUp;
|
|
|
|
switch (State.FPRoundingMode())
|
|
{
|
|
default:
|
|
case ARoundMode.ToNearest:
|
|
RoundUp = (Error > 0.5d || (Error == 0.5d && (IntMant & 1u) == 1u));
|
|
OverflowToInf = true;
|
|
break;
|
|
|
|
case ARoundMode.TowardsPlusInfinity:
|
|
RoundUp = (Error != 0d && !Sign);
|
|
OverflowToInf = !Sign;
|
|
break;
|
|
|
|
case ARoundMode.TowardsMinusInfinity:
|
|
RoundUp = (Error != 0d && Sign);
|
|
OverflowToInf = Sign;
|
|
break;
|
|
|
|
case ARoundMode.TowardsZero:
|
|
RoundUp = false;
|
|
OverflowToInf = false;
|
|
break;
|
|
}
|
|
|
|
if (RoundUp)
|
|
{
|
|
IntMant++;
|
|
|
|
if (IntMant == (uint)Math.Pow(2d, F))
|
|
{
|
|
BiasedExp = 1u;
|
|
}
|
|
|
|
if (IntMant == (uint)Math.Pow(2d, F + 1))
|
|
{
|
|
BiasedExp++;
|
|
IntMant >>= 1;
|
|
}
|
|
}
|
|
|
|
ushort ResultBits;
|
|
|
|
if (!State.GetFpcrFlag(FPCR.AHP))
|
|
{
|
|
if (BiasedExp >= (uint)Math.Pow(2d, E) - 1u)
|
|
{
|
|
ResultBits = OverflowToInf ? FPInfinity(Sign) : FPMaxNormal(Sign);
|
|
|
|
FPProcessException(FPExc.Overflow, State);
|
|
|
|
Error = 1d;
|
|
}
|
|
else
|
|
{
|
|
ResultBits = (ushort)((Sign ? 1u : 0u) << 15 | (BiasedExp & 0x1Fu) << 10 | (IntMant & 0x03FFu));
|
|
}
|
|
}
|
|
else
|
|
{
|
|
if (BiasedExp >= (uint)Math.Pow(2d, E))
|
|
{
|
|
ResultBits = (ushort)((Sign ? 1u : 0u) << 15 | 0x7FFFu);
|
|
|
|
FPProcessException(FPExc.InvalidOp, State);
|
|
|
|
Error = 0d;
|
|
}
|
|
else
|
|
{
|
|
ResultBits = (ushort)((Sign ? 1u : 0u) << 15 | (BiasedExp & 0x1Fu) << 10 | (IntMant & 0x03FFu));
|
|
}
|
|
}
|
|
|
|
if (Error != 0d)
|
|
{
|
|
FPProcessException(FPExc.Inexact, State);
|
|
}
|
|
|
|
return ResultBits;
|
|
}
|
|
|
|
private static ushort FPConvertNaN(uint ValueBits)
|
|
{
|
|
return (ushort)((ValueBits & 0x80000000u) >> 16 | 0x7E00u | (ValueBits & 0x003FE000u) >> 13);
|
|
}
|
|
|
|
private static void FPProcessException(FPExc Exc, AThreadState State)
|
|
{
|
|
int Enable = (int)Exc + 8;
|
|
|
|
if ((State.Fpcr & (1 << Enable)) != 0)
|
|
{
|
|
throw new NotImplementedException("floating-point trap handling");
|
|
}
|
|
else
|
|
{
|
|
State.Fpsr |= 1 << (int)Exc;
|
|
}
|
|
}
|
|
}
|
|
|
|
static class ASoftFloat_32
|
|
{
|
|
public static float FPAdd(float Value1, float Value2, AThreadState State)
|
|
{
|
|
Debug.WriteLineIf(State.Fpcr != 0, $"ASoftFloat_32.FPAdd: State.Fpcr = 0x{State.Fpcr:X8}");
|
|
|
|
Value1 = Value1.FPUnpack(out FPType Type1, out bool Sign1, out uint Op1);
|
|
Value2 = Value2.FPUnpack(out FPType Type2, out bool Sign2, out uint Op2);
|
|
|
|
float Result = FPProcessNaNs(Type1, Type2, Op1, Op2, State, out bool Done);
|
|
|
|
if (!Done)
|
|
{
|
|
bool Inf1 = Type1 == FPType.Infinity; bool Zero1 = Type1 == FPType.Zero;
|
|
bool Inf2 = Type2 == FPType.Infinity; bool Zero2 = Type2 == FPType.Zero;
|
|
|
|
if (Inf1 && Inf2 && Sign1 == !Sign2)
|
|
{
|
|
Result = FPDefaultNaN();
|
|
|
|
FPProcessException(FPExc.InvalidOp, State);
|
|
}
|
|
else if ((Inf1 && !Sign1) || (Inf2 && !Sign2))
|
|
{
|
|
Result = FPInfinity(false);
|
|
}
|
|
else if ((Inf1 && Sign1) || (Inf2 && Sign2))
|
|
{
|
|
Result = FPInfinity(true);
|
|
}
|
|
else if (Zero1 && Zero2 && Sign1 == Sign2)
|
|
{
|
|
Result = FPZero(Sign1);
|
|
}
|
|
else
|
|
{
|
|
Result = Value1 + Value2;
|
|
}
|
|
}
|
|
|
|
return Result;
|
|
}
|
|
|
|
public static float FPDiv(float Value1, float Value2, AThreadState State)
|
|
{
|
|
Debug.WriteLineIf(State.Fpcr != 0, $"ASoftFloat_32.FPDiv: State.Fpcr = 0x{State.Fpcr:X8}");
|
|
|
|
Value1 = Value1.FPUnpack(out FPType Type1, out bool Sign1, out uint Op1);
|
|
Value2 = Value2.FPUnpack(out FPType Type2, out bool Sign2, out uint Op2);
|
|
|
|
float Result = FPProcessNaNs(Type1, Type2, Op1, Op2, State, out bool Done);
|
|
|
|
if (!Done)
|
|
{
|
|
bool Inf1 = Type1 == FPType.Infinity; bool Zero1 = Type1 == FPType.Zero;
|
|
bool Inf2 = Type2 == FPType.Infinity; bool Zero2 = Type2 == FPType.Zero;
|
|
|
|
if ((Inf1 && Inf2) || (Zero1 && Zero2))
|
|
{
|
|
Result = FPDefaultNaN();
|
|
|
|
FPProcessException(FPExc.InvalidOp, State);
|
|
}
|
|
else if (Inf1 || Zero2)
|
|
{
|
|
Result = FPInfinity(Sign1 ^ Sign2);
|
|
|
|
if (!Inf1) FPProcessException(FPExc.DivideByZero, State);
|
|
}
|
|
else if (Zero1 || Inf2)
|
|
{
|
|
Result = FPZero(Sign1 ^ Sign2);
|
|
}
|
|
else
|
|
{
|
|
Result = Value1 / Value2;
|
|
}
|
|
}
|
|
|
|
return Result;
|
|
}
|
|
|
|
public static float FPMax(float Value1, float Value2, AThreadState State)
|
|
{
|
|
Debug.WriteLineIf(State.Fpcr != 0, $"ASoftFloat_32.FPMax: State.Fpcr = 0x{State.Fpcr:X8}");
|
|
|
|
Value1 = Value1.FPUnpack(out FPType Type1, out bool Sign1, out uint Op1);
|
|
Value2 = Value2.FPUnpack(out FPType Type2, out bool Sign2, out uint Op2);
|
|
|
|
float Result = FPProcessNaNs(Type1, Type2, Op1, Op2, State, out bool Done);
|
|
|
|
if (!Done)
|
|
{
|
|
if (Value1 > Value2)
|
|
{
|
|
if (Type1 == FPType.Infinity)
|
|
{
|
|
Result = FPInfinity(Sign1);
|
|
}
|
|
else if (Type1 == FPType.Zero)
|
|
{
|
|
Result = FPZero(Sign1 && Sign2);
|
|
}
|
|
else
|
|
{
|
|
Result = Value1;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
if (Type2 == FPType.Infinity)
|
|
{
|
|
Result = FPInfinity(Sign2);
|
|
}
|
|
else if (Type2 == FPType.Zero)
|
|
{
|
|
Result = FPZero(Sign1 && Sign2);
|
|
}
|
|
else
|
|
{
|
|
Result = Value2;
|
|
}
|
|
}
|
|
}
|
|
|
|
return Result;
|
|
}
|
|
|
|
public static float FPMaxNum(float Value1, float Value2, AThreadState State)
|
|
{
|
|
Debug.WriteIf(State.Fpcr != 0, "ASoftFloat_32.FPMaxNum: ");
|
|
|
|
Value1.FPUnpack(out FPType Type1, out _, out _);
|
|
Value2.FPUnpack(out FPType Type2, out _, out _);
|
|
|
|
if (Type1 == FPType.QNaN && Type2 != FPType.QNaN)
|
|
{
|
|
Value1 = FPInfinity(true);
|
|
}
|
|
else if (Type1 != FPType.QNaN && Type2 == FPType.QNaN)
|
|
{
|
|
Value2 = FPInfinity(true);
|
|
}
|
|
|
|
return FPMax(Value1, Value2, State);
|
|
}
|
|
|
|
public static float FPMin(float Value1, float Value2, AThreadState State)
|
|
{
|
|
Debug.WriteLineIf(State.Fpcr != 0, $"ASoftFloat_32.FPMin: State.Fpcr = 0x{State.Fpcr:X8}");
|
|
|
|
Value1 = Value1.FPUnpack(out FPType Type1, out bool Sign1, out uint Op1);
|
|
Value2 = Value2.FPUnpack(out FPType Type2, out bool Sign2, out uint Op2);
|
|
|
|
float Result = FPProcessNaNs(Type1, Type2, Op1, Op2, State, out bool Done);
|
|
|
|
if (!Done)
|
|
{
|
|
if (Value1 < Value2)
|
|
{
|
|
if (Type1 == FPType.Infinity)
|
|
{
|
|
Result = FPInfinity(Sign1);
|
|
}
|
|
else if (Type1 == FPType.Zero)
|
|
{
|
|
Result = FPZero(Sign1 || Sign2);
|
|
}
|
|
else
|
|
{
|
|
Result = Value1;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
if (Type2 == FPType.Infinity)
|
|
{
|
|
Result = FPInfinity(Sign2);
|
|
}
|
|
else if (Type2 == FPType.Zero)
|
|
{
|
|
Result = FPZero(Sign1 || Sign2);
|
|
}
|
|
else
|
|
{
|
|
Result = Value2;
|
|
}
|
|
}
|
|
}
|
|
|
|
return Result;
|
|
}
|
|
|
|
public static float FPMinNum(float Value1, float Value2, AThreadState State)
|
|
{
|
|
Debug.WriteIf(State.Fpcr != 0, "ASoftFloat_32.FPMinNum: ");
|
|
|
|
Value1.FPUnpack(out FPType Type1, out _, out _);
|
|
Value2.FPUnpack(out FPType Type2, out _, out _);
|
|
|
|
if (Type1 == FPType.QNaN && Type2 != FPType.QNaN)
|
|
{
|
|
Value1 = FPInfinity(false);
|
|
}
|
|
else if (Type1 != FPType.QNaN && Type2 == FPType.QNaN)
|
|
{
|
|
Value2 = FPInfinity(false);
|
|
}
|
|
|
|
return FPMin(Value1, Value2, State);
|
|
}
|
|
|
|
public static float FPMul(float Value1, float Value2, AThreadState State)
|
|
{
|
|
Debug.WriteLineIf(State.Fpcr != 0, $"ASoftFloat_32.FPMul: State.Fpcr = 0x{State.Fpcr:X8}");
|
|
|
|
Value1 = Value1.FPUnpack(out FPType Type1, out bool Sign1, out uint Op1);
|
|
Value2 = Value2.FPUnpack(out FPType Type2, out bool Sign2, out uint Op2);
|
|
|
|
float Result = FPProcessNaNs(Type1, Type2, Op1, Op2, State, out bool Done);
|
|
|
|
if (!Done)
|
|
{
|
|
bool Inf1 = Type1 == FPType.Infinity; bool Zero1 = Type1 == FPType.Zero;
|
|
bool Inf2 = Type2 == FPType.Infinity; bool Zero2 = Type2 == FPType.Zero;
|
|
|
|
if ((Inf1 && Zero2) || (Zero1 && Inf2))
|
|
{
|
|
Result = FPDefaultNaN();
|
|
|
|
FPProcessException(FPExc.InvalidOp, State);
|
|
}
|
|
else if (Inf1 || Inf2)
|
|
{
|
|
Result = FPInfinity(Sign1 ^ Sign2);
|
|
}
|
|
else if (Zero1 || Zero2)
|
|
{
|
|
Result = FPZero(Sign1 ^ Sign2);
|
|
}
|
|
else
|
|
{
|
|
Result = Value1 * Value2;
|
|
}
|
|
}
|
|
|
|
return Result;
|
|
}
|
|
|
|
public static float FPMulAdd(float ValueA, float Value1, float Value2, AThreadState State)
|
|
{
|
|
Debug.WriteLineIf(State.Fpcr != 0, $"ASoftFloat_32.FPMulAdd: State.Fpcr = 0x{State.Fpcr:X8}");
|
|
|
|
ValueA = ValueA.FPUnpack(out FPType TypeA, out bool SignA, out uint Addend);
|
|
Value1 = Value1.FPUnpack(out FPType Type1, out bool Sign1, out uint Op1);
|
|
Value2 = Value2.FPUnpack(out FPType Type2, out bool Sign2, out uint Op2);
|
|
|
|
bool Inf1 = Type1 == FPType.Infinity; bool Zero1 = Type1 == FPType.Zero;
|
|
bool Inf2 = Type2 == FPType.Infinity; bool Zero2 = Type2 == FPType.Zero;
|
|
|
|
float Result = FPProcessNaNs3(TypeA, Type1, Type2, Addend, Op1, Op2, State, out bool Done);
|
|
|
|
if (TypeA == FPType.QNaN && ((Inf1 && Zero2) || (Zero1 && Inf2)))
|
|
{
|
|
Result = FPDefaultNaN();
|
|
|
|
FPProcessException(FPExc.InvalidOp, State);
|
|
}
|
|
|
|
if (!Done)
|
|
{
|
|
bool InfA = TypeA == FPType.Infinity; bool ZeroA = TypeA == FPType.Zero;
|
|
|
|
bool SignP = Sign1 ^ Sign2;
|
|
bool InfP = Inf1 || Inf2;
|
|
bool ZeroP = Zero1 || Zero2;
|
|
|
|
if ((Inf1 && Zero2) || (Zero1 && Inf2) || (InfA && InfP && SignA != SignP))
|
|
{
|
|
Result = FPDefaultNaN();
|
|
|
|
FPProcessException(FPExc.InvalidOp, State);
|
|
}
|
|
else if ((InfA && !SignA) || (InfP && !SignP))
|
|
{
|
|
Result = FPInfinity(false);
|
|
}
|
|
else if ((InfA && SignA) || (InfP && SignP))
|
|
{
|
|
Result = FPInfinity(true);
|
|
}
|
|
else if (ZeroA && ZeroP && SignA == SignP)
|
|
{
|
|
Result = FPZero(SignA);
|
|
}
|
|
else
|
|
{
|
|
// TODO: When available, use: T MathF.FusedMultiplyAdd(T, T, T);
|
|
// https://github.com/dotnet/corefx/issues/31903
|
|
|
|
Result = ValueA + (Value1 * Value2);
|
|
}
|
|
}
|
|
|
|
return Result;
|
|
}
|
|
|
|
[MethodImpl(MethodImplOptions.AggressiveInlining)]
|
|
public static float FPMulSub(float ValueA, float Value1, float Value2, AThreadState State)
|
|
{
|
|
Debug.WriteIf(State.Fpcr != 0, "ASoftFloat_32.FPMulSub: ");
|
|
|
|
Value1 = Value1.FPNeg();
|
|
|
|
return FPMulAdd(ValueA, Value1, Value2, State);
|
|
}
|
|
|
|
public static float FPMulX(float Value1, float Value2, AThreadState State)
|
|
{
|
|
Debug.WriteLineIf(State.Fpcr != 0, $"ASoftFloat_32.FPMulX: State.Fpcr = 0x{State.Fpcr:X8}");
|
|
|
|
Value1 = Value1.FPUnpack(out FPType Type1, out bool Sign1, out uint Op1);
|
|
Value2 = Value2.FPUnpack(out FPType Type2, out bool Sign2, out uint Op2);
|
|
|
|
float Result = FPProcessNaNs(Type1, Type2, Op1, Op2, State, out bool Done);
|
|
|
|
if (!Done)
|
|
{
|
|
bool Inf1 = Type1 == FPType.Infinity; bool Zero1 = Type1 == FPType.Zero;
|
|
bool Inf2 = Type2 == FPType.Infinity; bool Zero2 = Type2 == FPType.Zero;
|
|
|
|
if ((Inf1 && Zero2) || (Zero1 && Inf2))
|
|
{
|
|
Result = FPTwo(Sign1 ^ Sign2);
|
|
}
|
|
else if (Inf1 || Inf2)
|
|
{
|
|
Result = FPInfinity(Sign1 ^ Sign2);
|
|
}
|
|
else if (Zero1 || Zero2)
|
|
{
|
|
Result = FPZero(Sign1 ^ Sign2);
|
|
}
|
|
else
|
|
{
|
|
Result = Value1 * Value2;
|
|
}
|
|
}
|
|
|
|
return Result;
|
|
}
|
|
|
|
public static float FPRecipStepFused(float Value1, float Value2, AThreadState State)
|
|
{
|
|
Debug.WriteLineIf(State.Fpcr != 0, $"ASoftFloat_32.FPRecipStepFused: State.Fpcr = 0x{State.Fpcr:X8}");
|
|
|
|
Value1 = Value1.FPNeg();
|
|
|
|
Value1 = Value1.FPUnpack(out FPType Type1, out bool Sign1, out uint Op1);
|
|
Value2 = Value2.FPUnpack(out FPType Type2, out bool Sign2, out uint Op2);
|
|
|
|
float Result = FPProcessNaNs(Type1, Type2, Op1, Op2, State, out bool Done);
|
|
|
|
if (!Done)
|
|
{
|
|
bool Inf1 = Type1 == FPType.Infinity; bool Zero1 = Type1 == FPType.Zero;
|
|
bool Inf2 = Type2 == FPType.Infinity; bool Zero2 = Type2 == FPType.Zero;
|
|
|
|
if ((Inf1 && Zero2) || (Zero1 && Inf2))
|
|
{
|
|
Result = FPTwo(false);
|
|
}
|
|
else if (Inf1 || Inf2)
|
|
{
|
|
Result = FPInfinity(Sign1 ^ Sign2);
|
|
}
|
|
else
|
|
{
|
|
// TODO: When available, use: T MathF.FusedMultiplyAdd(T, T, T);
|
|
// https://github.com/dotnet/corefx/issues/31903
|
|
|
|
Result = 2f + (Value1 * Value2);
|
|
}
|
|
}
|
|
|
|
return Result;
|
|
}
|
|
|
|
public static float FPRecpX(float Value, AThreadState State)
|
|
{
|
|
Debug.WriteLineIf(State.Fpcr != 0, $"ASoftFloat_32.FPRecpX: State.Fpcr = 0x{State.Fpcr:X8}");
|
|
|
|
Value.FPUnpack(out FPType Type, out bool Sign, out uint Op);
|
|
|
|
float Result;
|
|
|
|
if (Type == FPType.SNaN || Type == FPType.QNaN)
|
|
{
|
|
Result = FPProcessNaN(Type, Op, State);
|
|
}
|
|
else
|
|
{
|
|
uint NotExp = (~Op >> 23) & 0xFFu;
|
|
uint MaxExp = 0xFEu;
|
|
|
|
Result = BitConverter.Int32BitsToSingle(
|
|
(int)((Sign ? 1u : 0u) << 31 | (NotExp == 0xFFu ? MaxExp : NotExp) << 23));
|
|
}
|
|
|
|
return Result;
|
|
}
|
|
|
|
public static float FPRSqrtStepFused(float Value1, float Value2, AThreadState State)
|
|
{
|
|
Debug.WriteLineIf(State.Fpcr != 0, $"ASoftFloat_32.FPRSqrtStepFused: State.Fpcr = 0x{State.Fpcr:X8}");
|
|
|
|
Value1 = Value1.FPNeg();
|
|
|
|
Value1 = Value1.FPUnpack(out FPType Type1, out bool Sign1, out uint Op1);
|
|
Value2 = Value2.FPUnpack(out FPType Type2, out bool Sign2, out uint Op2);
|
|
|
|
float Result = FPProcessNaNs(Type1, Type2, Op1, Op2, State, out bool Done);
|
|
|
|
if (!Done)
|
|
{
|
|
bool Inf1 = Type1 == FPType.Infinity; bool Zero1 = Type1 == FPType.Zero;
|
|
bool Inf2 = Type2 == FPType.Infinity; bool Zero2 = Type2 == FPType.Zero;
|
|
|
|
if ((Inf1 && Zero2) || (Zero1 && Inf2))
|
|
{
|
|
Result = FPOnePointFive(false);
|
|
}
|
|
else if (Inf1 || Inf2)
|
|
{
|
|
Result = FPInfinity(Sign1 ^ Sign2);
|
|
}
|
|
else
|
|
{
|
|
// TODO: When available, use: T MathF.FusedMultiplyAdd(T, T, T);
|
|
// https://github.com/dotnet/corefx/issues/31903
|
|
|
|
Result = (3f + (Value1 * Value2)) / 2f;
|
|
}
|
|
}
|
|
|
|
return Result;
|
|
}
|
|
|
|
public static float FPSqrt(float Value, AThreadState State)
|
|
{
|
|
Debug.WriteLineIf(State.Fpcr != 0, $"ASoftFloat_32.FPSqrt: State.Fpcr = 0x{State.Fpcr:X8}");
|
|
|
|
Value = Value.FPUnpack(out FPType Type, out bool Sign, out uint Op);
|
|
|
|
float Result;
|
|
|
|
if (Type == FPType.SNaN || Type == FPType.QNaN)
|
|
{
|
|
Result = FPProcessNaN(Type, Op, State);
|
|
}
|
|
else if (Type == FPType.Zero)
|
|
{
|
|
Result = FPZero(Sign);
|
|
}
|
|
else if (Type == FPType.Infinity && !Sign)
|
|
{
|
|
Result = FPInfinity(Sign);
|
|
}
|
|
else if (Sign)
|
|
{
|
|
Result = FPDefaultNaN();
|
|
|
|
FPProcessException(FPExc.InvalidOp, State);
|
|
}
|
|
else
|
|
{
|
|
Result = MathF.Sqrt(Value);
|
|
}
|
|
|
|
return Result;
|
|
}
|
|
|
|
public static float FPSub(float Value1, float Value2, AThreadState State)
|
|
{
|
|
Debug.WriteLineIf(State.Fpcr != 0, $"ASoftFloat_32.FPSub: State.Fpcr = 0x{State.Fpcr:X8}");
|
|
|
|
Value1 = Value1.FPUnpack(out FPType Type1, out bool Sign1, out uint Op1);
|
|
Value2 = Value2.FPUnpack(out FPType Type2, out bool Sign2, out uint Op2);
|
|
|
|
float Result = FPProcessNaNs(Type1, Type2, Op1, Op2, State, out bool Done);
|
|
|
|
if (!Done)
|
|
{
|
|
bool Inf1 = Type1 == FPType.Infinity; bool Zero1 = Type1 == FPType.Zero;
|
|
bool Inf2 = Type2 == FPType.Infinity; bool Zero2 = Type2 == FPType.Zero;
|
|
|
|
if (Inf1 && Inf2 && Sign1 == Sign2)
|
|
{
|
|
Result = FPDefaultNaN();
|
|
|
|
FPProcessException(FPExc.InvalidOp, State);
|
|
}
|
|
else if ((Inf1 && !Sign1) || (Inf2 && Sign2))
|
|
{
|
|
Result = FPInfinity(false);
|
|
}
|
|
else if ((Inf1 && Sign1) || (Inf2 && !Sign2))
|
|
{
|
|
Result = FPInfinity(true);
|
|
}
|
|
else if (Zero1 && Zero2 && Sign1 == !Sign2)
|
|
{
|
|
Result = FPZero(Sign1);
|
|
}
|
|
else
|
|
{
|
|
Result = Value1 - Value2;
|
|
}
|
|
}
|
|
|
|
return Result;
|
|
}
|
|
|
|
private static float FPDefaultNaN()
|
|
{
|
|
return -float.NaN;
|
|
}
|
|
|
|
private static float FPInfinity(bool Sign)
|
|
{
|
|
return Sign ? float.NegativeInfinity : float.PositiveInfinity;
|
|
}
|
|
|
|
private static float FPZero(bool Sign)
|
|
{
|
|
return Sign ? -0f : +0f;
|
|
}
|
|
|
|
private static float FPTwo(bool Sign)
|
|
{
|
|
return Sign ? -2f : +2f;
|
|
}
|
|
|
|
private static float FPOnePointFive(bool Sign)
|
|
{
|
|
return Sign ? -1.5f : +1.5f;
|
|
}
|
|
|
|
private static float FPNeg(this float Value)
|
|
{
|
|
return -Value;
|
|
}
|
|
|
|
private static float FPUnpack(this float Value, out FPType Type, out bool Sign, out uint ValueBits)
|
|
{
|
|
ValueBits = (uint)BitConverter.SingleToInt32Bits(Value);
|
|
|
|
Sign = (~ValueBits & 0x80000000u) == 0u;
|
|
|
|
if ((ValueBits & 0x7F800000u) == 0u)
|
|
{
|
|
if ((ValueBits & 0x007FFFFFu) == 0u)
|
|
{
|
|
Type = FPType.Zero;
|
|
}
|
|
else
|
|
{
|
|
Type = FPType.Nonzero;
|
|
}
|
|
}
|
|
else if ((~ValueBits & 0x7F800000u) == 0u)
|
|
{
|
|
if ((ValueBits & 0x007FFFFFu) == 0u)
|
|
{
|
|
Type = FPType.Infinity;
|
|
}
|
|
else
|
|
{
|
|
Type = (~ValueBits & 0x00400000u) == 0u
|
|
? FPType.QNaN
|
|
: FPType.SNaN;
|
|
|
|
return FPZero(Sign);
|
|
}
|
|
}
|
|
else
|
|
{
|
|
Type = FPType.Nonzero;
|
|
}
|
|
|
|
return Value;
|
|
}
|
|
|
|
private static float FPProcessNaNs(
|
|
FPType Type1,
|
|
FPType Type2,
|
|
uint Op1,
|
|
uint Op2,
|
|
AThreadState State,
|
|
out bool Done)
|
|
{
|
|
Done = true;
|
|
|
|
if (Type1 == FPType.SNaN)
|
|
{
|
|
return FPProcessNaN(Type1, Op1, State);
|
|
}
|
|
else if (Type2 == FPType.SNaN)
|
|
{
|
|
return FPProcessNaN(Type2, Op2, State);
|
|
}
|
|
else if (Type1 == FPType.QNaN)
|
|
{
|
|
return FPProcessNaN(Type1, Op1, State);
|
|
}
|
|
else if (Type2 == FPType.QNaN)
|
|
{
|
|
return FPProcessNaN(Type2, Op2, State);
|
|
}
|
|
|
|
Done = false;
|
|
|
|
return FPZero(false);
|
|
}
|
|
|
|
private static float FPProcessNaNs3(
|
|
FPType Type1,
|
|
FPType Type2,
|
|
FPType Type3,
|
|
uint Op1,
|
|
uint Op2,
|
|
uint Op3,
|
|
AThreadState State,
|
|
out bool Done)
|
|
{
|
|
Done = true;
|
|
|
|
if (Type1 == FPType.SNaN)
|
|
{
|
|
return FPProcessNaN(Type1, Op1, State);
|
|
}
|
|
else if (Type2 == FPType.SNaN)
|
|
{
|
|
return FPProcessNaN(Type2, Op2, State);
|
|
}
|
|
else if (Type3 == FPType.SNaN)
|
|
{
|
|
return FPProcessNaN(Type3, Op3, State);
|
|
}
|
|
else if (Type1 == FPType.QNaN)
|
|
{
|
|
return FPProcessNaN(Type1, Op1, State);
|
|
}
|
|
else if (Type2 == FPType.QNaN)
|
|
{
|
|
return FPProcessNaN(Type2, Op2, State);
|
|
}
|
|
else if (Type3 == FPType.QNaN)
|
|
{
|
|
return FPProcessNaN(Type3, Op3, State);
|
|
}
|
|
|
|
Done = false;
|
|
|
|
return FPZero(false);
|
|
}
|
|
|
|
private static float FPProcessNaN(FPType Type, uint Op, AThreadState State)
|
|
{
|
|
if (Type == FPType.SNaN)
|
|
{
|
|
Op |= 1u << 22;
|
|
|
|
FPProcessException(FPExc.InvalidOp, State);
|
|
}
|
|
|
|
if (State.GetFpcrFlag(FPCR.DN))
|
|
{
|
|
return FPDefaultNaN();
|
|
}
|
|
|
|
return BitConverter.Int32BitsToSingle((int)Op);
|
|
}
|
|
|
|
private static void FPProcessException(FPExc Exc, AThreadState State)
|
|
{
|
|
int Enable = (int)Exc + 8;
|
|
|
|
if ((State.Fpcr & (1 << Enable)) != 0)
|
|
{
|
|
throw new NotImplementedException("floating-point trap handling");
|
|
}
|
|
else
|
|
{
|
|
State.Fpsr |= 1 << (int)Exc;
|
|
}
|
|
}
|
|
}
|
|
|
|
static class ASoftFloat_64
|
|
{
|
|
public static double FPAdd(double Value1, double Value2, AThreadState State)
|
|
{
|
|
Debug.WriteLineIf(State.Fpcr != 0, $"ASoftFloat_64.FPAdd: State.Fpcr = 0x{State.Fpcr:X8}");
|
|
|
|
Value1 = Value1.FPUnpack(out FPType Type1, out bool Sign1, out ulong Op1);
|
|
Value2 = Value2.FPUnpack(out FPType Type2, out bool Sign2, out ulong Op2);
|
|
|
|
double Result = FPProcessNaNs(Type1, Type2, Op1, Op2, State, out bool Done);
|
|
|
|
if (!Done)
|
|
{
|
|
bool Inf1 = Type1 == FPType.Infinity; bool Zero1 = Type1 == FPType.Zero;
|
|
bool Inf2 = Type2 == FPType.Infinity; bool Zero2 = Type2 == FPType.Zero;
|
|
|
|
if (Inf1 && Inf2 && Sign1 == !Sign2)
|
|
{
|
|
Result = FPDefaultNaN();
|
|
|
|
FPProcessException(FPExc.InvalidOp, State);
|
|
}
|
|
else if ((Inf1 && !Sign1) || (Inf2 && !Sign2))
|
|
{
|
|
Result = FPInfinity(false);
|
|
}
|
|
else if ((Inf1 && Sign1) || (Inf2 && Sign2))
|
|
{
|
|
Result = FPInfinity(true);
|
|
}
|
|
else if (Zero1 && Zero2 && Sign1 == Sign2)
|
|
{
|
|
Result = FPZero(Sign1);
|
|
}
|
|
else
|
|
{
|
|
Result = Value1 + Value2;
|
|
}
|
|
}
|
|
|
|
return Result;
|
|
}
|
|
|
|
public static double FPDiv(double Value1, double Value2, AThreadState State)
|
|
{
|
|
Debug.WriteLineIf(State.Fpcr != 0, $"ASoftFloat_64.FPDiv: State.Fpcr = 0x{State.Fpcr:X8}");
|
|
|
|
Value1 = Value1.FPUnpack(out FPType Type1, out bool Sign1, out ulong Op1);
|
|
Value2 = Value2.FPUnpack(out FPType Type2, out bool Sign2, out ulong Op2);
|
|
|
|
double Result = FPProcessNaNs(Type1, Type2, Op1, Op2, State, out bool Done);
|
|
|
|
if (!Done)
|
|
{
|
|
bool Inf1 = Type1 == FPType.Infinity; bool Zero1 = Type1 == FPType.Zero;
|
|
bool Inf2 = Type2 == FPType.Infinity; bool Zero2 = Type2 == FPType.Zero;
|
|
|
|
if ((Inf1 && Inf2) || (Zero1 && Zero2))
|
|
{
|
|
Result = FPDefaultNaN();
|
|
|
|
FPProcessException(FPExc.InvalidOp, State);
|
|
}
|
|
else if (Inf1 || Zero2)
|
|
{
|
|
Result = FPInfinity(Sign1 ^ Sign2);
|
|
|
|
if (!Inf1) FPProcessException(FPExc.DivideByZero, State);
|
|
}
|
|
else if (Zero1 || Inf2)
|
|
{
|
|
Result = FPZero(Sign1 ^ Sign2);
|
|
}
|
|
else
|
|
{
|
|
Result = Value1 / Value2;
|
|
}
|
|
}
|
|
|
|
return Result;
|
|
}
|
|
|
|
public static double FPMax(double Value1, double Value2, AThreadState State)
|
|
{
|
|
Debug.WriteLineIf(State.Fpcr != 0, $"ASoftFloat_64.FPMax: State.Fpcr = 0x{State.Fpcr:X8}");
|
|
|
|
Value1 = Value1.FPUnpack(out FPType Type1, out bool Sign1, out ulong Op1);
|
|
Value2 = Value2.FPUnpack(out FPType Type2, out bool Sign2, out ulong Op2);
|
|
|
|
double Result = FPProcessNaNs(Type1, Type2, Op1, Op2, State, out bool Done);
|
|
|
|
if (!Done)
|
|
{
|
|
if (Value1 > Value2)
|
|
{
|
|
if (Type1 == FPType.Infinity)
|
|
{
|
|
Result = FPInfinity(Sign1);
|
|
}
|
|
else if (Type1 == FPType.Zero)
|
|
{
|
|
Result = FPZero(Sign1 && Sign2);
|
|
}
|
|
else
|
|
{
|
|
Result = Value1;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
if (Type2 == FPType.Infinity)
|
|
{
|
|
Result = FPInfinity(Sign2);
|
|
}
|
|
else if (Type2 == FPType.Zero)
|
|
{
|
|
Result = FPZero(Sign1 && Sign2);
|
|
}
|
|
else
|
|
{
|
|
Result = Value2;
|
|
}
|
|
}
|
|
}
|
|
|
|
return Result;
|
|
}
|
|
|
|
public static double FPMaxNum(double Value1, double Value2, AThreadState State)
|
|
{
|
|
Debug.WriteIf(State.Fpcr != 0, "ASoftFloat_64.FPMaxNum: ");
|
|
|
|
Value1.FPUnpack(out FPType Type1, out _, out _);
|
|
Value2.FPUnpack(out FPType Type2, out _, out _);
|
|
|
|
if (Type1 == FPType.QNaN && Type2 != FPType.QNaN)
|
|
{
|
|
Value1 = FPInfinity(true);
|
|
}
|
|
else if (Type1 != FPType.QNaN && Type2 == FPType.QNaN)
|
|
{
|
|
Value2 = FPInfinity(true);
|
|
}
|
|
|
|
return FPMax(Value1, Value2, State);
|
|
}
|
|
|
|
public static double FPMin(double Value1, double Value2, AThreadState State)
|
|
{
|
|
Debug.WriteLineIf(State.Fpcr != 0, $"ASoftFloat_64.FPMin: State.Fpcr = 0x{State.Fpcr:X8}");
|
|
|
|
Value1 = Value1.FPUnpack(out FPType Type1, out bool Sign1, out ulong Op1);
|
|
Value2 = Value2.FPUnpack(out FPType Type2, out bool Sign2, out ulong Op2);
|
|
|
|
double Result = FPProcessNaNs(Type1, Type2, Op1, Op2, State, out bool Done);
|
|
|
|
if (!Done)
|
|
{
|
|
if (Value1 < Value2)
|
|
{
|
|
if (Type1 == FPType.Infinity)
|
|
{
|
|
Result = FPInfinity(Sign1);
|
|
}
|
|
else if (Type1 == FPType.Zero)
|
|
{
|
|
Result = FPZero(Sign1 || Sign2);
|
|
}
|
|
else
|
|
{
|
|
Result = Value1;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
if (Type2 == FPType.Infinity)
|
|
{
|
|
Result = FPInfinity(Sign2);
|
|
}
|
|
else if (Type2 == FPType.Zero)
|
|
{
|
|
Result = FPZero(Sign1 || Sign2);
|
|
}
|
|
else
|
|
{
|
|
Result = Value2;
|
|
}
|
|
}
|
|
}
|
|
|
|
return Result;
|
|
}
|
|
|
|
public static double FPMinNum(double Value1, double Value2, AThreadState State)
|
|
{
|
|
Debug.WriteIf(State.Fpcr != 0, "ASoftFloat_64.FPMinNum: ");
|
|
|
|
Value1.FPUnpack(out FPType Type1, out _, out _);
|
|
Value2.FPUnpack(out FPType Type2, out _, out _);
|
|
|
|
if (Type1 == FPType.QNaN && Type2 != FPType.QNaN)
|
|
{
|
|
Value1 = FPInfinity(false);
|
|
}
|
|
else if (Type1 != FPType.QNaN && Type2 == FPType.QNaN)
|
|
{
|
|
Value2 = FPInfinity(false);
|
|
}
|
|
|
|
return FPMin(Value1, Value2, State);
|
|
}
|
|
|
|
public static double FPMul(double Value1, double Value2, AThreadState State)
|
|
{
|
|
Debug.WriteLineIf(State.Fpcr != 0, $"ASoftFloat_64.FPMul: State.Fpcr = 0x{State.Fpcr:X8}");
|
|
|
|
Value1 = Value1.FPUnpack(out FPType Type1, out bool Sign1, out ulong Op1);
|
|
Value2 = Value2.FPUnpack(out FPType Type2, out bool Sign2, out ulong Op2);
|
|
|
|
double Result = FPProcessNaNs(Type1, Type2, Op1, Op2, State, out bool Done);
|
|
|
|
if (!Done)
|
|
{
|
|
bool Inf1 = Type1 == FPType.Infinity; bool Zero1 = Type1 == FPType.Zero;
|
|
bool Inf2 = Type2 == FPType.Infinity; bool Zero2 = Type2 == FPType.Zero;
|
|
|
|
if ((Inf1 && Zero2) || (Zero1 && Inf2))
|
|
{
|
|
Result = FPDefaultNaN();
|
|
|
|
FPProcessException(FPExc.InvalidOp, State);
|
|
}
|
|
else if (Inf1 || Inf2)
|
|
{
|
|
Result = FPInfinity(Sign1 ^ Sign2);
|
|
}
|
|
else if (Zero1 || Zero2)
|
|
{
|
|
Result = FPZero(Sign1 ^ Sign2);
|
|
}
|
|
else
|
|
{
|
|
Result = Value1 * Value2;
|
|
}
|
|
}
|
|
|
|
return Result;
|
|
}
|
|
|
|
public static double FPMulAdd(double ValueA, double Value1, double Value2, AThreadState State)
|
|
{
|
|
Debug.WriteLineIf(State.Fpcr != 0, $"ASoftFloat_64.FPMulAdd: State.Fpcr = 0x{State.Fpcr:X8}");
|
|
|
|
ValueA = ValueA.FPUnpack(out FPType TypeA, out bool SignA, out ulong Addend);
|
|
Value1 = Value1.FPUnpack(out FPType Type1, out bool Sign1, out ulong Op1);
|
|
Value2 = Value2.FPUnpack(out FPType Type2, out bool Sign2, out ulong Op2);
|
|
|
|
bool Inf1 = Type1 == FPType.Infinity; bool Zero1 = Type1 == FPType.Zero;
|
|
bool Inf2 = Type2 == FPType.Infinity; bool Zero2 = Type2 == FPType.Zero;
|
|
|
|
double Result = FPProcessNaNs3(TypeA, Type1, Type2, Addend, Op1, Op2, State, out bool Done);
|
|
|
|
if (TypeA == FPType.QNaN && ((Inf1 && Zero2) || (Zero1 && Inf2)))
|
|
{
|
|
Result = FPDefaultNaN();
|
|
|
|
FPProcessException(FPExc.InvalidOp, State);
|
|
}
|
|
|
|
if (!Done)
|
|
{
|
|
bool InfA = TypeA == FPType.Infinity; bool ZeroA = TypeA == FPType.Zero;
|
|
|
|
bool SignP = Sign1 ^ Sign2;
|
|
bool InfP = Inf1 || Inf2;
|
|
bool ZeroP = Zero1 || Zero2;
|
|
|
|
if ((Inf1 && Zero2) || (Zero1 && Inf2) || (InfA && InfP && SignA != SignP))
|
|
{
|
|
Result = FPDefaultNaN();
|
|
|
|
FPProcessException(FPExc.InvalidOp, State);
|
|
}
|
|
else if ((InfA && !SignA) || (InfP && !SignP))
|
|
{
|
|
Result = FPInfinity(false);
|
|
}
|
|
else if ((InfA && SignA) || (InfP && SignP))
|
|
{
|
|
Result = FPInfinity(true);
|
|
}
|
|
else if (ZeroA && ZeroP && SignA == SignP)
|
|
{
|
|
Result = FPZero(SignA);
|
|
}
|
|
else
|
|
{
|
|
// TODO: When available, use: T Math.FusedMultiplyAdd(T, T, T);
|
|
// https://github.com/dotnet/corefx/issues/31903
|
|
|
|
Result = ValueA + (Value1 * Value2);
|
|
}
|
|
}
|
|
|
|
return Result;
|
|
}
|
|
|
|
[MethodImpl(MethodImplOptions.AggressiveInlining)]
|
|
public static double FPMulSub(double ValueA, double Value1, double Value2, AThreadState State)
|
|
{
|
|
Debug.WriteIf(State.Fpcr != 0, "ASoftFloat_64.FPMulSub: ");
|
|
|
|
Value1 = Value1.FPNeg();
|
|
|
|
return FPMulAdd(ValueA, Value1, Value2, State);
|
|
}
|
|
|
|
public static double FPMulX(double Value1, double Value2, AThreadState State)
|
|
{
|
|
Debug.WriteLineIf(State.Fpcr != 0, $"ASoftFloat_64.FPMulX: State.Fpcr = 0x{State.Fpcr:X8}");
|
|
|
|
Value1 = Value1.FPUnpack(out FPType Type1, out bool Sign1, out ulong Op1);
|
|
Value2 = Value2.FPUnpack(out FPType Type2, out bool Sign2, out ulong Op2);
|
|
|
|
double Result = FPProcessNaNs(Type1, Type2, Op1, Op2, State, out bool Done);
|
|
|
|
if (!Done)
|
|
{
|
|
bool Inf1 = Type1 == FPType.Infinity; bool Zero1 = Type1 == FPType.Zero;
|
|
bool Inf2 = Type2 == FPType.Infinity; bool Zero2 = Type2 == FPType.Zero;
|
|
|
|
if ((Inf1 && Zero2) || (Zero1 && Inf2))
|
|
{
|
|
Result = FPTwo(Sign1 ^ Sign2);
|
|
}
|
|
else if (Inf1 || Inf2)
|
|
{
|
|
Result = FPInfinity(Sign1 ^ Sign2);
|
|
}
|
|
else if (Zero1 || Zero2)
|
|
{
|
|
Result = FPZero(Sign1 ^ Sign2);
|
|
}
|
|
else
|
|
{
|
|
Result = Value1 * Value2;
|
|
}
|
|
}
|
|
|
|
return Result;
|
|
}
|
|
|
|
public static double FPRecipStepFused(double Value1, double Value2, AThreadState State)
|
|
{
|
|
Debug.WriteLineIf(State.Fpcr != 0, $"ASoftFloat_64.FPRecipStepFused: State.Fpcr = 0x{State.Fpcr:X8}");
|
|
|
|
Value1 = Value1.FPNeg();
|
|
|
|
Value1 = Value1.FPUnpack(out FPType Type1, out bool Sign1, out ulong Op1);
|
|
Value2 = Value2.FPUnpack(out FPType Type2, out bool Sign2, out ulong Op2);
|
|
|
|
double Result = FPProcessNaNs(Type1, Type2, Op1, Op2, State, out bool Done);
|
|
|
|
if (!Done)
|
|
{
|
|
bool Inf1 = Type1 == FPType.Infinity; bool Zero1 = Type1 == FPType.Zero;
|
|
bool Inf2 = Type2 == FPType.Infinity; bool Zero2 = Type2 == FPType.Zero;
|
|
|
|
if ((Inf1 && Zero2) || (Zero1 && Inf2))
|
|
{
|
|
Result = FPTwo(false);
|
|
}
|
|
else if (Inf1 || Inf2)
|
|
{
|
|
Result = FPInfinity(Sign1 ^ Sign2);
|
|
}
|
|
else
|
|
{
|
|
// TODO: When available, use: T Math.FusedMultiplyAdd(T, T, T);
|
|
// https://github.com/dotnet/corefx/issues/31903
|
|
|
|
Result = 2d + (Value1 * Value2);
|
|
}
|
|
}
|
|
|
|
return Result;
|
|
}
|
|
|
|
public static double FPRecpX(double Value, AThreadState State)
|
|
{
|
|
Debug.WriteLineIf(State.Fpcr != 0, $"ASoftFloat_64.FPRecpX: State.Fpcr = 0x{State.Fpcr:X8}");
|
|
|
|
Value.FPUnpack(out FPType Type, out bool Sign, out ulong Op);
|
|
|
|
double Result;
|
|
|
|
if (Type == FPType.SNaN || Type == FPType.QNaN)
|
|
{
|
|
Result = FPProcessNaN(Type, Op, State);
|
|
}
|
|
else
|
|
{
|
|
ulong NotExp = (~Op >> 52) & 0x7FFul;
|
|
ulong MaxExp = 0x7FEul;
|
|
|
|
Result = BitConverter.Int64BitsToDouble(
|
|
(long)((Sign ? 1ul : 0ul) << 63 | (NotExp == 0x7FFul ? MaxExp : NotExp) << 52));
|
|
}
|
|
|
|
return Result;
|
|
}
|
|
|
|
public static double FPRSqrtStepFused(double Value1, double Value2, AThreadState State)
|
|
{
|
|
Debug.WriteLineIf(State.Fpcr != 0, $"ASoftFloat_64.FPRSqrtStepFused: State.Fpcr = 0x{State.Fpcr:X8}");
|
|
|
|
Value1 = Value1.FPNeg();
|
|
|
|
Value1 = Value1.FPUnpack(out FPType Type1, out bool Sign1, out ulong Op1);
|
|
Value2 = Value2.FPUnpack(out FPType Type2, out bool Sign2, out ulong Op2);
|
|
|
|
double Result = FPProcessNaNs(Type1, Type2, Op1, Op2, State, out bool Done);
|
|
|
|
if (!Done)
|
|
{
|
|
bool Inf1 = Type1 == FPType.Infinity; bool Zero1 = Type1 == FPType.Zero;
|
|
bool Inf2 = Type2 == FPType.Infinity; bool Zero2 = Type2 == FPType.Zero;
|
|
|
|
if ((Inf1 && Zero2) || (Zero1 && Inf2))
|
|
{
|
|
Result = FPOnePointFive(false);
|
|
}
|
|
else if (Inf1 || Inf2)
|
|
{
|
|
Result = FPInfinity(Sign1 ^ Sign2);
|
|
}
|
|
else
|
|
{
|
|
// TODO: When available, use: T Math.FusedMultiplyAdd(T, T, T);
|
|
// https://github.com/dotnet/corefx/issues/31903
|
|
|
|
Result = (3d + (Value1 * Value2)) / 2d;
|
|
}
|
|
}
|
|
|
|
return Result;
|
|
}
|
|
|
|
public static double FPSqrt(double Value, AThreadState State)
|
|
{
|
|
Debug.WriteLineIf(State.Fpcr != 0, $"ASoftFloat_64.FPSqrt: State.Fpcr = 0x{State.Fpcr:X8}");
|
|
|
|
Value = Value.FPUnpack(out FPType Type, out bool Sign, out ulong Op);
|
|
|
|
double Result;
|
|
|
|
if (Type == FPType.SNaN || Type == FPType.QNaN)
|
|
{
|
|
Result = FPProcessNaN(Type, Op, State);
|
|
}
|
|
else if (Type == FPType.Zero)
|
|
{
|
|
Result = FPZero(Sign);
|
|
}
|
|
else if (Type == FPType.Infinity && !Sign)
|
|
{
|
|
Result = FPInfinity(Sign);
|
|
}
|
|
else if (Sign)
|
|
{
|
|
Result = FPDefaultNaN();
|
|
|
|
FPProcessException(FPExc.InvalidOp, State);
|
|
}
|
|
else
|
|
{
|
|
Result = Math.Sqrt(Value);
|
|
}
|
|
|
|
return Result;
|
|
}
|
|
|
|
public static double FPSub(double Value1, double Value2, AThreadState State)
|
|
{
|
|
Debug.WriteLineIf(State.Fpcr != 0, $"ASoftFloat_64.FPSub: State.Fpcr = 0x{State.Fpcr:X8}");
|
|
|
|
Value1 = Value1.FPUnpack(out FPType Type1, out bool Sign1, out ulong Op1);
|
|
Value2 = Value2.FPUnpack(out FPType Type2, out bool Sign2, out ulong Op2);
|
|
|
|
double Result = FPProcessNaNs(Type1, Type2, Op1, Op2, State, out bool Done);
|
|
|
|
if (!Done)
|
|
{
|
|
bool Inf1 = Type1 == FPType.Infinity; bool Zero1 = Type1 == FPType.Zero;
|
|
bool Inf2 = Type2 == FPType.Infinity; bool Zero2 = Type2 == FPType.Zero;
|
|
|
|
if (Inf1 && Inf2 && Sign1 == Sign2)
|
|
{
|
|
Result = FPDefaultNaN();
|
|
|
|
FPProcessException(FPExc.InvalidOp, State);
|
|
}
|
|
else if ((Inf1 && !Sign1) || (Inf2 && Sign2))
|
|
{
|
|
Result = FPInfinity(false);
|
|
}
|
|
else if ((Inf1 && Sign1) || (Inf2 && !Sign2))
|
|
{
|
|
Result = FPInfinity(true);
|
|
}
|
|
else if (Zero1 && Zero2 && Sign1 == !Sign2)
|
|
{
|
|
Result = FPZero(Sign1);
|
|
}
|
|
else
|
|
{
|
|
Result = Value1 - Value2;
|
|
}
|
|
}
|
|
|
|
return Result;
|
|
}
|
|
|
|
private static double FPDefaultNaN()
|
|
{
|
|
return -double.NaN;
|
|
}
|
|
|
|
private static double FPInfinity(bool Sign)
|
|
{
|
|
return Sign ? double.NegativeInfinity : double.PositiveInfinity;
|
|
}
|
|
|
|
private static double FPZero(bool Sign)
|
|
{
|
|
return Sign ? -0d : +0d;
|
|
}
|
|
|
|
private static double FPTwo(bool Sign)
|
|
{
|
|
return Sign ? -2d : +2d;
|
|
}
|
|
|
|
private static double FPOnePointFive(bool Sign)
|
|
{
|
|
return Sign ? -1.5d : +1.5d;
|
|
}
|
|
|
|
private static double FPNeg(this double Value)
|
|
{
|
|
return -Value;
|
|
}
|
|
|
|
private static double FPUnpack(this double Value, out FPType Type, out bool Sign, out ulong ValueBits)
|
|
{
|
|
ValueBits = (ulong)BitConverter.DoubleToInt64Bits(Value);
|
|
|
|
Sign = (~ValueBits & 0x8000000000000000ul) == 0ul;
|
|
|
|
if ((ValueBits & 0x7FF0000000000000ul) == 0ul)
|
|
{
|
|
if ((ValueBits & 0x000FFFFFFFFFFFFFul) == 0ul)
|
|
{
|
|
Type = FPType.Zero;
|
|
}
|
|
else
|
|
{
|
|
Type = FPType.Nonzero;
|
|
}
|
|
}
|
|
else if ((~ValueBits & 0x7FF0000000000000ul) == 0ul)
|
|
{
|
|
if ((ValueBits & 0x000FFFFFFFFFFFFFul) == 0ul)
|
|
{
|
|
Type = FPType.Infinity;
|
|
}
|
|
else
|
|
{
|
|
Type = (~ValueBits & 0x0008000000000000ul) == 0ul
|
|
? FPType.QNaN
|
|
: FPType.SNaN;
|
|
|
|
return FPZero(Sign);
|
|
}
|
|
}
|
|
else
|
|
{
|
|
Type = FPType.Nonzero;
|
|
}
|
|
|
|
return Value;
|
|
}
|
|
|
|
private static double FPProcessNaNs(
|
|
FPType Type1,
|
|
FPType Type2,
|
|
ulong Op1,
|
|
ulong Op2,
|
|
AThreadState State,
|
|
out bool Done)
|
|
{
|
|
Done = true;
|
|
|
|
if (Type1 == FPType.SNaN)
|
|
{
|
|
return FPProcessNaN(Type1, Op1, State);
|
|
}
|
|
else if (Type2 == FPType.SNaN)
|
|
{
|
|
return FPProcessNaN(Type2, Op2, State);
|
|
}
|
|
else if (Type1 == FPType.QNaN)
|
|
{
|
|
return FPProcessNaN(Type1, Op1, State);
|
|
}
|
|
else if (Type2 == FPType.QNaN)
|
|
{
|
|
return FPProcessNaN(Type2, Op2, State);
|
|
}
|
|
|
|
Done = false;
|
|
|
|
return FPZero(false);
|
|
}
|
|
|
|
private static double FPProcessNaNs3(
|
|
FPType Type1,
|
|
FPType Type2,
|
|
FPType Type3,
|
|
ulong Op1,
|
|
ulong Op2,
|
|
ulong Op3,
|
|
AThreadState State,
|
|
out bool Done)
|
|
{
|
|
Done = true;
|
|
|
|
if (Type1 == FPType.SNaN)
|
|
{
|
|
return FPProcessNaN(Type1, Op1, State);
|
|
}
|
|
else if (Type2 == FPType.SNaN)
|
|
{
|
|
return FPProcessNaN(Type2, Op2, State);
|
|
}
|
|
else if (Type3 == FPType.SNaN)
|
|
{
|
|
return FPProcessNaN(Type3, Op3, State);
|
|
}
|
|
else if (Type1 == FPType.QNaN)
|
|
{
|
|
return FPProcessNaN(Type1, Op1, State);
|
|
}
|
|
else if (Type2 == FPType.QNaN)
|
|
{
|
|
return FPProcessNaN(Type2, Op2, State);
|
|
}
|
|
else if (Type3 == FPType.QNaN)
|
|
{
|
|
return FPProcessNaN(Type3, Op3, State);
|
|
}
|
|
|
|
Done = false;
|
|
|
|
return FPZero(false);
|
|
}
|
|
|
|
private static double FPProcessNaN(FPType Type, ulong Op, AThreadState State)
|
|
{
|
|
if (Type == FPType.SNaN)
|
|
{
|
|
Op |= 1ul << 51;
|
|
|
|
FPProcessException(FPExc.InvalidOp, State);
|
|
}
|
|
|
|
if (State.GetFpcrFlag(FPCR.DN))
|
|
{
|
|
return FPDefaultNaN();
|
|
}
|
|
|
|
return BitConverter.Int64BitsToDouble((long)Op);
|
|
}
|
|
|
|
private static void FPProcessException(FPExc Exc, AThreadState State)
|
|
{
|
|
int Enable = (int)Exc + 8;
|
|
|
|
if ((State.Fpcr & (1 << Enable)) != 0)
|
|
{
|
|
throw new NotImplementedException("floating-point trap handling");
|
|
}
|
|
else
|
|
{
|
|
State.Fpsr |= 1 << (int)Exc;
|
|
}
|
|
}
|
|
}
|
|
}
|