mirror of
https://github.com/ryujinx-mirror/ryujinx.git
synced 2024-12-23 16:25:45 +00:00
17620d18db
* ARMeilleure: Add AVX512{F,VL,DQ,BW} detection
Add `UseAvx512Ortho` and `UseAvx512OrthoFloat` optimization flags as
short-hands for `F+VL` and `F+VL+DQ`.
* ARMeilleure: Add initial support for EVEX instruction encoding
Does not implement rounding, or exception controls.
* ARMeilleure: Add `X86Vpternlogd`
Accelerates the vector-`Not` instruction.
* ARMeilleure: Add check for `OSXSAVE` for AVX{2,512}
* ARMeilleure: Add check for `XCR0` flags
Add XCR0 register checks for AVX and AVX512F, following the guidelines
from section 14.3 and 15.2 from the Intel Architecture Software
Developer's Manual.
* ARMeilleure: Remove redundant `ReProtect` and `Dispose`, formatting
* ARMeilleure: Move XCR0 procedure to GetXcr0Eax
* ARMeilleure: Add `XCR0` to `FeatureInfo` structure
* ARMeilleure: Utilize `ReadOnlySpan` for Xcr0 assembly
Avoids an additional allocation
* ARMeilleure: Formatting fixes
* ARMeilleure: Fix EVEX encoding src2 register index
> Just like in VEX prefix, vvvv is provided in inverted form.
* ARMeilleure: Add `X86Vpternlogd` acceleration to `Vmvn_I`
Passes unit tests, verified instruction utilization
* ARMeilleure: Fix EVEX register operand designations
Operand 2 was being sourced improperly.
EVEX encoded instructions source their operands like so:
Operand 1: ModRM:reg
Operand 2: EVEX.vvvvv
Operand 3: ModRM:r/m
Operand 4: Imm
This fixes the improper register designations when emitting vpternlog.
Now "dest", "src1", "src2" arguments emit in the proper order in EVEX instructions.
* ARMeilleure: Add `X86Vpternlogd` acceleration to `Orn_V`
* ARMeilleure: PTC version bump
* ARMeilleure: Update EVEX encoding Debug.Assert to Debug.Fail
* ARMeilleure: Update EVEX encoding comment capitalization
612 lines
20 KiB
C#
612 lines
20 KiB
C#
using ARMeilleure.Decoders;
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using ARMeilleure.IntermediateRepresentation;
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using ARMeilleure.Translation;
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using System;
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using System.Diagnostics;
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using static ARMeilleure.Instructions.InstEmitHelper;
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using static ARMeilleure.Instructions.InstEmitSimdHelper;
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using static ARMeilleure.IntermediateRepresentation.Operand.Factory;
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namespace ARMeilleure.Instructions
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{
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static partial class InstEmit
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{
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public static void And_V(ArmEmitterContext context)
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{
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if (Optimizations.UseAdvSimd)
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{
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InstEmitSimdHelperArm64.EmitVectorBinaryOp(context, Intrinsic.Arm64AndV);
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}
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else if (Optimizations.UseSse2)
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{
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OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
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Operand n = GetVec(op.Rn);
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Operand m = GetVec(op.Rm);
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Operand res = context.AddIntrinsic(Intrinsic.X86Pand, n, m);
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if (op.RegisterSize == RegisterSize.Simd64)
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{
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res = context.VectorZeroUpper64(res);
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}
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context.Copy(GetVec(op.Rd), res);
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}
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else
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{
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EmitVectorBinaryOpZx(context, (op1, op2) => context.BitwiseAnd(op1, op2));
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}
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}
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public static void Bic_V(ArmEmitterContext context)
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{
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if (Optimizations.UseAdvSimd)
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{
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InstEmitSimdHelperArm64.EmitVectorBinaryOp(context, Intrinsic.Arm64BicV);
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}
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else if (Optimizations.UseSse2)
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{
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OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
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Operand n = GetVec(op.Rn);
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Operand m = GetVec(op.Rm);
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Operand res = context.AddIntrinsic(Intrinsic.X86Pandn, m, n);
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if (op.RegisterSize == RegisterSize.Simd64)
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{
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res = context.VectorZeroUpper64(res);
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}
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context.Copy(GetVec(op.Rd), res);
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}
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else
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{
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EmitVectorBinaryOpZx(context, (op1, op2) =>
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{
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return context.BitwiseAnd(op1, context.BitwiseNot(op2));
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});
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}
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}
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public static void Bic_Vi(ArmEmitterContext context)
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{
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if (Optimizations.UseSse2)
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{
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OpCodeSimdImm op = (OpCodeSimdImm)context.CurrOp;
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int eSize = 8 << op.Size;
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Operand d = GetVec(op.Rd);
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Operand imm = eSize switch {
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16 => X86GetAllElements(context, (short)~op.Immediate),
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32 => X86GetAllElements(context, (int)~op.Immediate),
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_ => throw new InvalidOperationException($"Invalid element size {eSize}.")
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};
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Operand res = context.AddIntrinsic(Intrinsic.X86Pand, d, imm);
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if (op.RegisterSize == RegisterSize.Simd64)
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{
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res = context.VectorZeroUpper64(res);
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}
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context.Copy(GetVec(op.Rd), res);
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}
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else
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{
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EmitVectorImmBinaryOp(context, (op1, op2) =>
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{
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return context.BitwiseAnd(op1, context.BitwiseNot(op2));
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});
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}
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}
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public static void Bif_V(ArmEmitterContext context)
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{
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if (Optimizations.UseAdvSimd)
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{
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InstEmitSimdHelperArm64.EmitVectorTernaryOpRd(context, Intrinsic.Arm64BifV);
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}
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else
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{
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EmitBifBit(context, notRm: true);
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}
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}
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public static void Bit_V(ArmEmitterContext context)
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{
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if (Optimizations.UseAdvSimd)
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{
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InstEmitSimdHelperArm64.EmitVectorTernaryOpRd(context, Intrinsic.Arm64BitV);
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}
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else
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{
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EmitBifBit(context, notRm: false);
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}
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}
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private static void EmitBifBit(ArmEmitterContext context, bool notRm)
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{
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OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
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if (Optimizations.UseSse2)
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{
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Operand d = GetVec(op.Rd);
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Operand n = GetVec(op.Rn);
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Operand m = GetVec(op.Rm);
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Operand res = context.AddIntrinsic(Intrinsic.X86Pxor, n, d);
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if (notRm)
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{
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res = context.AddIntrinsic(Intrinsic.X86Pandn, m, res);
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}
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else
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{
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res = context.AddIntrinsic(Intrinsic.X86Pand, m, res);
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}
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res = context.AddIntrinsic(Intrinsic.X86Pxor, d, res);
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if (op.RegisterSize == RegisterSize.Simd64)
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{
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res = context.VectorZeroUpper64(res);
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}
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context.Copy(d, res);
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}
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else
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{
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Operand res = context.VectorZero();
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int elems = op.RegisterSize == RegisterSize.Simd128 ? 2 : 1;
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for (int index = 0; index < elems; index++)
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{
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Operand d = EmitVectorExtractZx(context, op.Rd, index, 3);
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Operand n = EmitVectorExtractZx(context, op.Rn, index, 3);
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Operand m = EmitVectorExtractZx(context, op.Rm, index, 3);
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if (notRm)
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{
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m = context.BitwiseNot(m);
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}
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Operand e = context.BitwiseExclusiveOr(d, n);
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e = context.BitwiseAnd(e, m);
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e = context.BitwiseExclusiveOr(e, d);
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res = EmitVectorInsert(context, res, e, index, 3);
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}
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context.Copy(GetVec(op.Rd), res);
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}
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}
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public static void Bsl_V(ArmEmitterContext context)
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{
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if (Optimizations.UseAdvSimd)
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{
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InstEmitSimdHelperArm64.EmitVectorTernaryOpRd(context, Intrinsic.Arm64BslV);
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}
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else if (Optimizations.UseSse2)
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{
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OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
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Operand d = GetVec(op.Rd);
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Operand n = GetVec(op.Rn);
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Operand m = GetVec(op.Rm);
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Operand res = context.AddIntrinsic(Intrinsic.X86Pxor, n, m);
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res = context.AddIntrinsic(Intrinsic.X86Pand, res, d);
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res = context.AddIntrinsic(Intrinsic.X86Pxor, res, m);
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if (op.RegisterSize == RegisterSize.Simd64)
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{
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res = context.VectorZeroUpper64(res);
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}
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context.Copy(d, res);
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}
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else
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{
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EmitVectorTernaryOpZx(context, (op1, op2, op3) =>
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{
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return context.BitwiseExclusiveOr(
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context.BitwiseAnd(op1,
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context.BitwiseExclusiveOr(op2, op3)), op3);
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});
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}
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}
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public static void Eor_V(ArmEmitterContext context)
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{
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if (Optimizations.UseAdvSimd)
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{
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InstEmitSimdHelperArm64.EmitVectorBinaryOp(context, Intrinsic.Arm64EorV);
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}
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else if (Optimizations.UseSse2)
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{
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OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
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Operand n = GetVec(op.Rn);
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Operand m = GetVec(op.Rm);
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Operand res = context.AddIntrinsic(Intrinsic.X86Pxor, n, m);
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if (op.RegisterSize == RegisterSize.Simd64)
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{
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res = context.VectorZeroUpper64(res);
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}
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context.Copy(GetVec(op.Rd), res);
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}
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else
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{
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EmitVectorBinaryOpZx(context, (op1, op2) => context.BitwiseExclusiveOr(op1, op2));
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}
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}
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public static void Not_V(ArmEmitterContext context)
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{
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if (Optimizations.UseAvx512Ortho)
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{
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OpCodeSimd op = (OpCodeSimd)context.CurrOp;
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Operand n = GetVec(op.Rn);
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Operand res = context.AddIntrinsic(Intrinsic.X86Vpternlogd, n, n, Const(~0b10101010));
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if (op.RegisterSize == RegisterSize.Simd64)
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{
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res = context.VectorZeroUpper64(res);
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}
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context.Copy(GetVec(op.Rd), res);
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}
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else if (Optimizations.UseSse2)
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{
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OpCodeSimd op = (OpCodeSimd)context.CurrOp;
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Operand n = GetVec(op.Rn);
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Operand mask = X86GetAllElements(context, -1L);
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Operand res = context.AddIntrinsic(Intrinsic.X86Pandn, n, mask);
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if (op.RegisterSize == RegisterSize.Simd64)
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{
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res = context.VectorZeroUpper64(res);
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}
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context.Copy(GetVec(op.Rd), res);
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}
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else
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{
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EmitVectorUnaryOpZx(context, (op1) => context.BitwiseNot(op1));
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}
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}
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public static void Orn_V(ArmEmitterContext context)
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{
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if (Optimizations.UseAdvSimd)
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{
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InstEmitSimdHelperArm64.EmitVectorBinaryOp(context, Intrinsic.Arm64OrnV);
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}
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else if (Optimizations.UseAvx512Ortho)
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{
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OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
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Operand n = GetVec(op.Rn);
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Operand m = GetVec(op.Rm);
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Operand res = context.AddIntrinsic(Intrinsic.X86Vpternlogd, n, m, Const(0b11001100 | ~0b10101010));
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if (op.RegisterSize == RegisterSize.Simd64)
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{
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res = context.VectorZeroUpper64(res);
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}
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context.Copy(GetVec(op.Rd), res);
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}
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else if (Optimizations.UseSse2)
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{
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OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
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Operand n = GetVec(op.Rn);
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Operand m = GetVec(op.Rm);
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Operand mask = X86GetAllElements(context, -1L);
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Operand res = context.AddIntrinsic(Intrinsic.X86Pandn, m, mask);
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res = context.AddIntrinsic(Intrinsic.X86Por, res, n);
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if (op.RegisterSize == RegisterSize.Simd64)
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{
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res = context.VectorZeroUpper64(res);
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}
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context.Copy(GetVec(op.Rd), res);
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}
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else
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{
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EmitVectorBinaryOpZx(context, (op1, op2) =>
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{
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return context.BitwiseOr(op1, context.BitwiseNot(op2));
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});
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}
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}
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public static void Orr_V(ArmEmitterContext context)
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{
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if (Optimizations.UseAdvSimd)
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{
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InstEmitSimdHelperArm64.EmitVectorBinaryOp(context, Intrinsic.Arm64OrrV);
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}
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else if (Optimizations.UseSse2)
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{
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OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
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Operand n = GetVec(op.Rn);
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Operand m = GetVec(op.Rm);
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Operand res = context.AddIntrinsic(Intrinsic.X86Por, n, m);
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if (op.RegisterSize == RegisterSize.Simd64)
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{
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res = context.VectorZeroUpper64(res);
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}
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context.Copy(GetVec(op.Rd), res);
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}
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else
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{
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EmitVectorBinaryOpZx(context, (op1, op2) => context.BitwiseOr(op1, op2));
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}
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}
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public static void Orr_Vi(ArmEmitterContext context)
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{
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if (Optimizations.UseSse2)
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{
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OpCodeSimdImm op = (OpCodeSimdImm)context.CurrOp;
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int eSize = 8 << op.Size;
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Operand d = GetVec(op.Rd);
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Operand imm = eSize switch {
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16 => X86GetAllElements(context, (short)op.Immediate),
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32 => X86GetAllElements(context, (int)op.Immediate),
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_ => throw new InvalidOperationException($"Invalid element size {eSize}.")
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};
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Operand res = context.AddIntrinsic(Intrinsic.X86Por, d, imm);
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if (op.RegisterSize == RegisterSize.Simd64)
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{
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res = context.VectorZeroUpper64(res);
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}
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context.Copy(GetVec(op.Rd), res);
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}
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else
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{
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EmitVectorImmBinaryOp(context, (op1, op2) => context.BitwiseOr(op1, op2));
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}
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}
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public static void Rbit_V(ArmEmitterContext context)
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{
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OpCodeSimd op = (OpCodeSimd)context.CurrOp;
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if (Optimizations.UseGfni)
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{
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const long bitMatrix =
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(0b10000000L << 56) |
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(0b01000000L << 48) |
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(0b00100000L << 40) |
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(0b00010000L << 32) |
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(0b00001000L << 24) |
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(0b00000100L << 16) |
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(0b00000010L << 8) |
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(0b00000001L << 0);
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Operand vBitMatrix = X86GetAllElements(context, bitMatrix);
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Operand res = context.AddIntrinsic(Intrinsic.X86Gf2p8affineqb, GetVec(op.Rn), vBitMatrix, Const(0));
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if (op.RegisterSize == RegisterSize.Simd64)
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{
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res = context.VectorZeroUpper64(res);
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}
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context.Copy(GetVec(op.Rd), res);
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}
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else
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{
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Operand res = context.VectorZero();
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int elems = op.RegisterSize == RegisterSize.Simd128 ? 16 : 8;
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for (int index = 0; index < elems; index++)
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{
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Operand ne = EmitVectorExtractZx(context, op.Rn, index, 0);
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Operand de = EmitReverseBits8Op(context, ne);
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res = EmitVectorInsert(context, res, de, index, 0);
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}
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context.Copy(GetVec(op.Rd), res);
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}
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}
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private static Operand EmitReverseBits8Op(ArmEmitterContext context, Operand op)
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{
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Debug.Assert(op.Type == OperandType.I64);
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Operand val = context.BitwiseOr(context.ShiftRightUI(context.BitwiseAnd(op, Const(0xaaul)), Const(1)),
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context.ShiftLeft (context.BitwiseAnd(op, Const(0x55ul)), Const(1)));
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val = context.BitwiseOr(context.ShiftRightUI(context.BitwiseAnd(val, Const(0xccul)), Const(2)),
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context.ShiftLeft (context.BitwiseAnd(val, Const(0x33ul)), Const(2)));
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return context.BitwiseOr(context.ShiftRightUI(val, Const(4)),
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context.ShiftLeft (context.BitwiseAnd(val, Const(0x0ful)), Const(4)));
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}
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public static void Rev16_V(ArmEmitterContext context)
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{
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if (Optimizations.UseSsse3)
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{
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OpCodeSimd op = (OpCodeSimd)context.CurrOp;
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Operand n = GetVec(op.Rn);
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const long maskE0 = 06L << 56 | 07L << 48 | 04L << 40 | 05L << 32 | 02L << 24 | 03L << 16 | 00L << 8 | 01L << 0;
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const long maskE1 = 14L << 56 | 15L << 48 | 12L << 40 | 13L << 32 | 10L << 24 | 11L << 16 | 08L << 8 | 09L << 0;
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Operand mask = X86GetScalar(context, maskE0);
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mask = EmitVectorInsert(context, mask, Const(maskE1), 1, 3);
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Operand res = context.AddIntrinsic(Intrinsic.X86Pshufb, n, mask);
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if (op.RegisterSize == RegisterSize.Simd64)
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{
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res = context.VectorZeroUpper64(res);
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}
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context.Copy(GetVec(op.Rd), res);
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}
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else
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{
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EmitRev_V(context, containerSize: 1);
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}
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}
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public static void Rev32_V(ArmEmitterContext context)
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{
|
|
if (Optimizations.UseSsse3)
|
|
{
|
|
OpCodeSimd op = (OpCodeSimd)context.CurrOp;
|
|
|
|
Operand n = GetVec(op.Rn);
|
|
|
|
Operand mask;
|
|
|
|
if (op.Size == 0)
|
|
{
|
|
const long maskE0 = 04L << 56 | 05L << 48 | 06L << 40 | 07L << 32 | 00L << 24 | 01L << 16 | 02L << 8 | 03L << 0;
|
|
const long maskE1 = 12L << 56 | 13L << 48 | 14L << 40 | 15L << 32 | 08L << 24 | 09L << 16 | 10L << 8 | 11L << 0;
|
|
|
|
mask = X86GetScalar(context, maskE0);
|
|
|
|
mask = EmitVectorInsert(context, mask, Const(maskE1), 1, 3);
|
|
}
|
|
else /* if (op.Size == 1) */
|
|
{
|
|
const long maskE0 = 05L << 56 | 04L << 48 | 07L << 40 | 06L << 32 | 01L << 24 | 00L << 16 | 03L << 8 | 02L << 0;
|
|
const long maskE1 = 13L << 56 | 12L << 48 | 15L << 40 | 14L << 32 | 09L << 24 | 08L << 16 | 11L << 8 | 10L << 0;
|
|
|
|
mask = X86GetScalar(context, maskE0);
|
|
|
|
mask = EmitVectorInsert(context, mask, Const(maskE1), 1, 3);
|
|
}
|
|
|
|
Operand res = context.AddIntrinsic(Intrinsic.X86Pshufb, n, mask);
|
|
|
|
if (op.RegisterSize == RegisterSize.Simd64)
|
|
{
|
|
res = context.VectorZeroUpper64(res);
|
|
}
|
|
|
|
context.Copy(GetVec(op.Rd), res);
|
|
}
|
|
else
|
|
{
|
|
EmitRev_V(context, containerSize: 2);
|
|
}
|
|
}
|
|
|
|
public static void Rev64_V(ArmEmitterContext context)
|
|
{
|
|
if (Optimizations.UseSsse3)
|
|
{
|
|
OpCodeSimd op = (OpCodeSimd)context.CurrOp;
|
|
|
|
Operand n = GetVec(op.Rn);
|
|
|
|
Operand mask;
|
|
|
|
if (op.Size == 0)
|
|
{
|
|
const long maskE0 = 00L << 56 | 01L << 48 | 02L << 40 | 03L << 32 | 04L << 24 | 05L << 16 | 06L << 8 | 07L << 0;
|
|
const long maskE1 = 08L << 56 | 09L << 48 | 10L << 40 | 11L << 32 | 12L << 24 | 13L << 16 | 14L << 8 | 15L << 0;
|
|
|
|
mask = X86GetScalar(context, maskE0);
|
|
|
|
mask = EmitVectorInsert(context, mask, Const(maskE1), 1, 3);
|
|
}
|
|
else if (op.Size == 1)
|
|
{
|
|
const long maskE0 = 01L << 56 | 00L << 48 | 03L << 40 | 02L << 32 | 05L << 24 | 04L << 16 | 07L << 8 | 06L << 0;
|
|
const long maskE1 = 09L << 56 | 08L << 48 | 11L << 40 | 10L << 32 | 13L << 24 | 12L << 16 | 15L << 8 | 14L << 0;
|
|
|
|
mask = X86GetScalar(context, maskE0);
|
|
|
|
mask = EmitVectorInsert(context, mask, Const(maskE1), 1, 3);
|
|
}
|
|
else /* if (op.Size == 2) */
|
|
{
|
|
const long maskE0 = 03L << 56 | 02L << 48 | 01L << 40 | 00L << 32 | 07L << 24 | 06L << 16 | 05L << 8 | 04L << 0;
|
|
const long maskE1 = 11L << 56 | 10L << 48 | 09L << 40 | 08L << 32 | 15L << 24 | 14L << 16 | 13L << 8 | 12L << 0;
|
|
|
|
mask = X86GetScalar(context, maskE0);
|
|
|
|
mask = EmitVectorInsert(context, mask, Const(maskE1), 1, 3);
|
|
}
|
|
|
|
Operand res = context.AddIntrinsic(Intrinsic.X86Pshufb, n, mask);
|
|
|
|
if (op.RegisterSize == RegisterSize.Simd64)
|
|
{
|
|
res = context.VectorZeroUpper64(res);
|
|
}
|
|
|
|
context.Copy(GetVec(op.Rd), res);
|
|
}
|
|
else
|
|
{
|
|
EmitRev_V(context, containerSize: 3);
|
|
}
|
|
}
|
|
|
|
private static void EmitRev_V(ArmEmitterContext context, int containerSize)
|
|
{
|
|
OpCodeSimd op = (OpCodeSimd)context.CurrOp;
|
|
|
|
Operand res = context.VectorZero();
|
|
|
|
int elems = op.GetBytesCount() >> op.Size;
|
|
|
|
int containerMask = (1 << (containerSize - op.Size)) - 1;
|
|
|
|
for (int index = 0; index < elems; index++)
|
|
{
|
|
int revIndex = index ^ containerMask;
|
|
|
|
Operand ne = EmitVectorExtractZx(context, op.Rn, revIndex, op.Size);
|
|
|
|
res = EmitVectorInsert(context, res, ne, index, op.Size);
|
|
}
|
|
|
|
context.Copy(GetVec(op.Rd), res);
|
|
}
|
|
}
|
|
}
|