mirror of
https://github.com/ryujinx-mirror/ryujinx.git
synced 2024-12-24 01:05:45 +00:00
36b9ab0e48
* Remove ARM32 interpreter and add ARM32 support on the translator * Nits. * Rename Cond -> Condition * Align code again * Rename Data to Alu * Enable ARM32 support and handle undefined instructions * Use the IsThumb method to check if its a thumb opcode * Remove another 32-bits check
163 lines
No EOL
4.4 KiB
C#
163 lines
No EOL
4.4 KiB
C#
using ChocolArm64.Decoders;
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using ChocolArm64.State;
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using ChocolArm64.Translation;
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using System.Reflection.Emit;
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namespace ChocolArm64.Instructions
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{
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static partial class InstEmit
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{
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public static void B(ILEmitterCtx context)
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{
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OpCodeBImmAl64 op = (OpCodeBImmAl64)context.CurrOp;
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if (context.CurrBlock.Branch != null)
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{
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context.Emit(OpCodes.Br, context.GetLabel(op.Imm));
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}
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else
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{
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context.EmitStoreState();
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context.EmitLdc_I8(op.Imm);
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context.Emit(OpCodes.Ret);
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}
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}
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public static void B_Cond(ILEmitterCtx context)
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{
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OpCodeBImmCond64 op = (OpCodeBImmCond64)context.CurrOp;
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EmitBranch(context, op.Cond);
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}
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public static void Bl(ILEmitterCtx context)
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{
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OpCodeBImmAl64 op = (OpCodeBImmAl64)context.CurrOp;
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context.EmitLdc_I(op.Position + 4);
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context.EmitStint(RegisterAlias.Lr);
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context.EmitStoreState();
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InstEmitFlowHelper.EmitCall(context, op.Imm);
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}
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public static void Blr(ILEmitterCtx context)
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{
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OpCodeBReg64 op = (OpCodeBReg64)context.CurrOp;
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context.EmitLdintzr(op.Rn);
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context.EmitLdc_I(op.Position + 4);
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context.EmitStint(RegisterAlias.Lr);
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context.EmitStoreState();
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context.Emit(OpCodes.Ret);
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}
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public static void Br(ILEmitterCtx context)
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{
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OpCodeBReg64 op = (OpCodeBReg64)context.CurrOp;
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context.EmitStoreState();
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context.EmitLdintzr(op.Rn);
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context.Emit(OpCodes.Ret);
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}
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public static void Cbnz(ILEmitterCtx context) => EmitCb(context, OpCodes.Bne_Un);
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public static void Cbz(ILEmitterCtx context) => EmitCb(context, OpCodes.Beq);
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private static void EmitCb(ILEmitterCtx context, OpCode ilOp)
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{
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OpCodeBImmCmp64 op = (OpCodeBImmCmp64)context.CurrOp;
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context.EmitLdintzr(op.Rt);
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context.EmitLdc_I(0);
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EmitBranch(context, ilOp);
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}
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public static void Ret(ILEmitterCtx context)
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{
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context.EmitStoreState();
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context.EmitLdint(RegisterAlias.Lr);
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context.Emit(OpCodes.Ret);
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}
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public static void Tbnz(ILEmitterCtx context) => EmitTb(context, OpCodes.Bne_Un);
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public static void Tbz(ILEmitterCtx context) => EmitTb(context, OpCodes.Beq);
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private static void EmitTb(ILEmitterCtx context, OpCode ilOp)
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{
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OpCodeBImmTest64 op = (OpCodeBImmTest64)context.CurrOp;
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context.EmitLdintzr(op.Rt);
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context.EmitLdc_I(1L << op.Pos);
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context.Emit(OpCodes.And);
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context.EmitLdc_I(0);
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EmitBranch(context, ilOp);
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}
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private static void EmitBranch(ILEmitterCtx context, Condition cond)
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{
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OpCodeBImm64 op = (OpCodeBImm64)context.CurrOp;
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if (context.CurrBlock.Next != null &&
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context.CurrBlock.Branch != null)
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{
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context.EmitCondBranch(context.GetLabel(op.Imm), cond);
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}
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else
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{
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context.EmitStoreState();
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ILLabel lblTaken = new ILLabel();
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context.EmitCondBranch(lblTaken, cond);
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context.EmitLdc_I8(op.Position + 4);
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context.Emit(OpCodes.Ret);
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context.MarkLabel(lblTaken);
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context.EmitLdc_I8(op.Imm);
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context.Emit(OpCodes.Ret);
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}
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}
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private static void EmitBranch(ILEmitterCtx context, OpCode ilOp)
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{
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OpCodeBImm64 op = (OpCodeBImm64)context.CurrOp;
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if (context.CurrBlock.Next != null &&
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context.CurrBlock.Branch != null)
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{
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context.Emit(ilOp, context.GetLabel(op.Imm));
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}
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else
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{
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context.EmitStoreState();
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ILLabel lblTaken = new ILLabel();
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context.Emit(ilOp, lblTaken);
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context.EmitLdc_I8(op.Position + 4);
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context.Emit(OpCodes.Ret);
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context.MarkLabel(lblTaken);
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context.EmitLdc_I8(op.Imm);
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context.Emit(OpCodes.Ret);
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}
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}
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}
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} |