99 lines
4.2 KiB
C
99 lines
4.2 KiB
C
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#ifndef _HGIC_FWINFO_H_
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#define _HGIC_FWINFO_H_
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#include "../hgic.h"
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#define HGIC_FWINFO_BOOT_HDR 0x5a69
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#define HGIC_FWINFO_SPI_HDR 0x1
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#define HGIC_FWINFO_CODE_HDR 0x2
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struct hgic_spiflash_header_boot {
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u16 boot_flag; /* 0 : 0x5a69, header boot flag */
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u8 version; /* 2 : version */
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u8 size; /* 3 : Link to Next Header */
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u32 boot_to_sram_addr; /* 4 : spi data load to sram addr */
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u32 run_sram_addr; /* 8 : code execute start addr */
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u32 boot_code_offset_addr; /* 12 : HeaderLen+ParamLen=4096+512 */
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u32 boot_from_flash_len; /* 16 : */
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u16 boot_data_crc; /* 20 : boot data crc check */
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u16 flash_blk_size; /* 22 : flash size in 64KB(version > 1), 512B(version== 0) */
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u16 boot_baud_mhz : 14, /* 24 : spi clk freq in mhz(version > 1), khz(version== 0) */
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driver_strength : 2; /* io driver strength */
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struct {
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u16 pll_src : 8, /* pll src in Mhz */
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pll_en : 1, /* PLL enable */
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debug : 1, /* debug info uart output enable */
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aes_en : 1, /* AES enable */
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crc_en : 1, /* CRC check enable */
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reserved : 4;
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} mode; /* 26 : boot option */
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u16 reserved; /* 28 : */
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u16 head_crc16; /* (size+4) byte CRC16 check value */
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}__packed;
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struct hgic_spiflash_read_cfg {
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u8 read_cmd; /* read_cmd */
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u8 cmd_dummy_cycles : 4, /* read dummy cycles */
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clock_mode : 2, /* clock polarity & phase */
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spec_sequnce_en : 1, /* spec sequnce to execute, maybe same with quad_wire_en */
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quad_wire_en : 1; /* spi D2/D3 enable */
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u8 wire_mode_cmd : 2,
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wire_mode_addr : 2,
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wire_mode_data : 2,
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quad_wire_select : 2; /* spi D2/D3 group select */
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u8 reserved3;
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u16 sample_delay; /* RX sample dalay time: 0 ~ clk_divor */
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}__packed;
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struct hgic_spiflash_header_spi_info {
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u8 func_code; /* 0 : header function(0x1) */
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u8 size; /* 1: Link to Next Header */
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struct hgic_spiflash_read_cfg read_cfg;
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u8 hgic_spiflash_spec_sequnce[64];
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u16 header_crc16; /* (size+2) byte CRC16 check value */
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}__packed;
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/* hgic_ah_fw_v1.0.1.1_2020.2.20.bin ？*/
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struct hgic_spiflash_header_firmware_info {
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u8 func_code; /* 0 : header function(0x2) */
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u8 size; /* 1: Link to Next Header */
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u32 sdk_version; /* version */
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u32 svn_version;
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u32 date; /* date */
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u16 chip_id; /* chip_id */
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u8 cpu_id; /* cpu id, fix 0 */
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u32 code_crc32; /* code CRC32 */
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u16 param_crc16; /* param CRC16 */
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u16 crc16; /* (size+2) byte CRC16 check value */
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}__packed;
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struct hgic_fw_info_hdr {
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struct hgic_spiflash_header_boot boot;
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struct hgic_spiflash_header_spi_info spi_infor; /* func1*/
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struct hgic_spiflash_header_firmware_info fw_infor ; /* func2*/
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} __packed;
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u16 hgic_crc16(const u8 *data, u32 length);
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u32 hgic_crc32(const u8 *data, u32 length);
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u16 hgic_get_fw_aes_en(const u8 *data, s32 *err_code);
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u16 hgic_get_fw_crc_en(const u8 *data, s32 *err_code);
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u32 hgic_get_fw_dl_addr(const u8 *data, s32 *err_code);
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u32 hgic_get_fw_run_addr(const u8 *data, s32 *err_code);
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u32 hgic_get_fw_code_offset(const u8 *data, s32 *err_code);
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u32 hgic_get_fw_local_crc32(const u8 *data, s32 *err_code);
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u32 hgic_get_fw_sdk_version(const u8 *data, s32 *err_code);
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u32 hgic_get_fw_svn_version(const u8 *data, s32 *err_code);
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u16 hgic_get_fw_chipid(const u8 *data, s32 *err_code);
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u8 hgic_get_fw_cpuid(const u8 *data, s32 *err_code);
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s32 hgic_get_fw_code_checksum(const u8 *data,s32 len);
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#endif
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