2023-05-16 09:13:19 +00:00
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#ifndef _HGIC_UTILS_H_
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#define _HGIC_UTILS_H_
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#define AC_NUM 4
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#define MAX_CHANS_NUM 16
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struct hgic_fwstat_chaninfo {
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u32 freq;
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u8 pri_chan;
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s8 bgrssi_min;
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s8 bgrssi_max;
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s8 bgrssi_avg;
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s32 bgrssi_acc;
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s32 cnt;
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s32 rxsync_cnt;
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s32 noise_factor;
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};
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struct hgic_fwstat_testmode {
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u32 test_tx_start : 1, bss_freq : 24;
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s32 freq_dev;
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s32 chip_temp;
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s32 tx_frms;
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s32 tx_fail;
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s32 tx_mcs;
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s32 tx_sig_bw;
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s32 rx_pkts;
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s32 rx_firm;
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s32 rx_err;
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s32 rx_rssi;
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s32 agc;
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s32 rx_evm;
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u8 chip_vcc[8];
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};
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struct hgic_fwstat_qa {
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u8 dut_mac[6];
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u16 svn_version;
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s8 result_per;
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s8 cfg_per;
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s8 rssi;
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s8 tssi;
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s8 rx_evm;
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s8 tx_evm;
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s8 rx_freq_dev;
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s8 tx_freq_dev;
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s8 rx_rssi_th;
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s8 tx_tssi_th;
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s8 rx_evm_th;
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s8 tx_evm_th;
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s8 rx_freq_dev_th;
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s8 tx_freq_dev_th;
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};
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struct hgic_fwstat_stainfo {
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u8 addr[6];
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s32 tx_frms;
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s32 tx_frms_success;
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s32 tx_cnt;
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s32 tx_apep;
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s32 tx_cca;
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s32 tx_apep_success;
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s32 tx_apep_droped;
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s32 tx_frms_droped;
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s32 tx_symbols;
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s32 freq_offset;
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u32 rx_cnt;
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u32 rx_pkts;
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u32 rx_bytes;
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u32 rx_fcs_err;
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u32 rx_symbols;
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u8 tx_bw : 3, tx_mcs : 4;
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u8 rx_bw : 4, rx_mcs : 4;
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s8 evm_avg, evm_std, rssi, tx_snr;
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u16 aid, agc;
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u16 fade_bw_ind[4];
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u64 tx_jiffies;
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};
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struct hgic_fwstat {
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u8 mode;
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u8 mac_address[6];
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u16 aid;
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u32 bss_freq_idx : 8, bss_freq : 24;
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u32 pri1m_start : 16, pri2m_start : 16;
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u32 pri1m_mid : 16, pri2m_mid : 16;
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u32 sec2m_mid : 16, sec4m_mid : 16;
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u32 pri1m_ed : 16, pri2m_ed : 16;
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u32 sec2m_ed : 16, sec4m_ed : 16;
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u8 tx_power_auto_adjust_en : 1, tx_pwr_adj : 5;
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u8 chan_cnt;
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u8 rx_duty_cycle;
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u8 tx_pwr;
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s8 bg_rssi;
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s32 bgrssi_iqacc;
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s32 demod_dly_max;
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s32 sifs_dly_max;
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s32 resp_dly_max;
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s32 resp_sifs_to;
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s32 resp_ack_to;
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s32 frms_ack_to;
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s32 rx_ovf_cnt;
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s32 rx_nobuf_cnt;
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s32 rx_bus_max;
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s16 bgrssi_spur_thd;
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s16 bgrssi_spur_det;
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s16 bgrssi_spurs;
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s16 bgrssi_iqmax;
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s16 rx_dc_i;
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s16 rx_dc_q;
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u32 lo_kick_cnt : 16, chan_switch_cnt : 16;
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s32 soft_rest;
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u32 lmac_txsq_count;
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u32 lmac_txq_count;
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u32 lmac_acq_count[AC_NUM];
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u32 lmac_txagg_count[AC_NUM];
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u32 lmac_statq_count;
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s32 lmac_rx_data_queue_count;
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s32 ac_irq_cnt;
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s32 ac_dly_max;
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s32 tx_irq_rts;
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s32 bo_irq_cnt[AC_NUM];
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s32 cts_tmo_cnt;
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s32 resp_tmo_cnt;
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s32 rx_irq_cnt;
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s32 tx_cnt;
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s32 tx_cts_bw_acc;
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s32 tx_cts_cnt;
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s32 tx_cts_evm_acc;
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s32 tx_frms;
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s32 tx_sq_empty;
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s32 agg_no_data;
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s32 agg_check_fail;
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s32 tx_apep;
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s32 tx_symbols;
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s32 tx_cca;
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s32 tx_fail;
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s32 tx_drop;
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s32 rx_cnt;
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s32 rx_cts_bw_acc;
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s32 rx_cts_cnt;
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s32 rx_cts_mcs_acc;
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s32 rx_pkts;
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s32 rx_bytes;
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s32 rx_symbols;
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s32 rx_phy_err;
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s32 rx_fcs_err;
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s32 phy_err_code;
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s32 tx_irq_bkn;
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u8 lmac_doze : 1, cca_obsv_dur : 3;
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s32 sta_tx_syms;
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s32 sta_rx_syms;
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u32 est_tx_bitrate;
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u32 sta_num;
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u8 fixed_tx_mcs;
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int skb_free_count;
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struct hgic_fwstat_chaninfo chan_list[MAX_CHANS_NUM];
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struct hgic_fwstat_testmode test_mode;
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struct hgic_fwstat_qa qa_stat;
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struct hgic_fwstat_stainfo sta_info[0];
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};
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char *hgic_fwstat_print(u8 *stat_buf);
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2023-10-12 23:37:43 +00:00
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int hgic_skip_padding(u8 *data);
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2023-05-16 09:13:19 +00:00
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int hgic_aligned_padding(struct sk_buff *skb);
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void hgic_print_hex(char *buf, int len);
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int hgic_config_read_u32_array(char *conf, char *field, u32 *arr, int count);
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int hgic_config_read_u16_array(char *conf, char *field, u16 *arr, int count);
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int hgic_config_read_str(char *conf, char *field, char *str, int size);
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int hgic_config_read_int(char *conf, char *field);
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void hgic_clear_queue(struct sk_buff_head *q);
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int hgic_hex2num(char c);
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2023-10-12 23:37:43 +00:00
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void hgic_strip_tail(char *str, u32 len);
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2023-05-16 09:13:19 +00:00
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int hgic_hex2byte(const char *hex);
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int hgic_pick_macaddr(char *mac_str, u8 *addr);
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#endif
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