gdkchan
|
595e7ee588
|
Add FCVTAS and FCVTAU instructions
|
2018-02-17 18:59:37 -03:00 |
|
gdkchan
|
161193e113
|
CPU refactoring - move SIMD (scalar and vector) instructions to separate files by category, remove AILConv and use only the methods inside SIMD helper to extract/insert vector elements
|
2018-02-17 18:06:11 -03:00 |
|
Merry
|
1bfe6a9c22
|
Add some tests (#18)
* Add tests
* Add some simple Alu instruction tests
* travis: Run tests
* CpuTest: Add TearDown
|
2018-02-15 21:04:38 -03:00 |
|
gdkchan
|
be1d01bf7d
|
Shouldn't have undone this
|
2018-02-15 01:35:44 -03:00 |
|
gdkchan
|
7c314eadcf
|
Emit CIL directly for more SIMD instructions, add UCVTF (vector, scalar) and UZP2, fix XTN (?)
|
2018-02-15 01:32:25 -03:00 |
|
Merry
|
7c4346685c
|
AInstEmitAluHelper: Simplify EmitAddsVCheck (#14)
|
2018-02-14 19:01:36 -03:00 |
|
Merry
|
7791e1fe36
|
AInstEmitAluHelper: Simplify EmitSubsCCheck (#15)
|
2018-02-14 19:01:21 -03:00 |
|
gdkchan
|
7ed1153062
|
Add SHRN instruction, and fix ADDV
|
2018-02-14 02:43:21 -03:00 |
|
gdkchan
|
f68696dc4a
|
Made initial implementation of the thread scheduler, refactor Svc to avoid passing many arguments
|
2018-02-13 23:43:08 -03:00 |
|
gdkchan
|
7d11a146c0
|
Generate CIL for SCVTF (vector), add undefined encodings for some instructions
|
2018-02-12 00:37:20 -03:00 |
|
gdkchan
|
55743c0cba
|
Only throw undefined instruction exception at execution, not at translation stage
|
2018-02-10 14:20:46 -03:00 |
|
gdkchan
|
9f612682e0
|
Add BRK on the opcode table
|
2018-02-10 12:16:48 -03:00 |
|
gdkchan
|
9063766ed6
|
Add BRK instruction, fix wrong namespace on one of Am interfaces, and disable Debug/Trace logs by default
|
2018-02-10 10:24:16 -03:00 |
|
gdkchan
|
7f4a190665
|
Fixes to memory management
|
2018-02-09 21:13:18 -03:00 |
|
gdkchan
|
ccc9ce1908
|
Move a few more SIMD instructions to emit CIL directly instead of a method call
|
2018-02-09 17:14:47 -03:00 |
|
gdkchan
|
6a3aa6cd88
|
Add FVCTZS (fixed point variant) and LD1 (single structure variant) instructions
|
2018-02-09 00:26:20 -03:00 |
|
gdkchan
|
ae91da5b60
|
Merge pull request #2 from gdkchan/direct_memory
Removed parts of the MMU functionality to use memory directly (faster…
|
2018-02-08 20:20:01 -03:00 |
|
gdkchan
|
64d34f2882
|
Fix a copy-paste bug on Ins_V
|
2018-02-07 21:53:23 -03:00 |
|
gdkchan
|
d0954564cd
|
Add ADC and SBC instructions
|
2018-02-07 20:46:36 -03:00 |
|
gdkchan
|
79f028e410
|
Add FMADD and FMSUB instructions
|
2018-02-07 20:07:16 -03:00 |
|
gdkchan
|
768b573772
|
Add FMOV (scalar, register) and FCMPE instructions
|
2018-02-07 19:43:52 -03:00 |
|
gdkchan
|
18ac1c4045
|
Removed parts of the MMU functionality to use memory directly (faster, but potentially more dangerous, WIP), also changed the Shl/Sshr immediate instructions to use IL instead of calling the method
|
2018-02-07 13:44:48 -03:00 |
|
gdkchan
|
d77d691381
|
Implement SSHL instruction, fix exception on FMAX/FMIN, and use a better exception message for undefined/unimplemented instructions
|
2018-02-07 09:38:43 -03:00 |
|
gdkchan
|
b99e808791
|
Support loading NSO/NRO without a MOD0 header, stub some functions, support more ids on SvcGetInfo
|
2018-02-06 20:28:32 -03:00 |
|
gdkchan
|
2347c44bbf
|
Improve access to system registers by using properties, also use exclusive region granularity on exclusive load/stores, and ensure that acquires without releases won't hold the address forever, remove unused ALU rev method
|
2018-02-06 12:15:08 -03:00 |
|
gdkchan
|
b7e1d9930d
|
aloha
|
2018-02-04 20:08:20 -03:00 |
|